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Dr. Hiroyuki Ohshima CSO/Deputy CTO, Japan Display Inc. “Mobile Display Technologies - Past, Present and Future-” Date: Nov. 11 (Tue), 2014 |
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Dr. Jack Sun VP/CTO, TSMC, Taiwan “Semiconductor Innovation into the Next Decade” Date: Nov. 12 (Wed), 2014 |
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Dr. Alex Jinsung Choi EVP/Head of ICT R&D, SKT, Korea “Internet of Things: Evolution towards a Hyper-Connected Society” Date: Nov. 11 (Tue), 2014 |
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Dr. Vivek De Fellow/Director, Intel, USA “Energy Efficient Computing in Nanoscale CMOS: Challenges and Opportunities” Date: Nov. 12 (Wed), 2014 |
| Title | Mobile Display Technologies -Past, Present and Future- | |
| Speaker | Mr. Hiroyuki Ohshima | |
| Position | Chief Strategy Officer and Deputy CTO | |
| Affiliation | Japan Display Inc. , Japan | |
| Time/Place | 08:50-09:35 Nov. 11 (Tue), 2014/Diamond II, 41F | |
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Biography: Mr. Ohshima completed his BS degree from Tokyo University in 1979, and joined Seiko Epson. He has been engaged in TFT LCD technologies and the FPD industry for more than 30 years. In 1983, he developed high-temperature poly-Si TFT (HTPS) and applied it to the world's first color TFT LCD. It was his first achievement in his TFT history, and was presented at SID in 1983. Later, he redirected his R&D efforts towards development of low-temperature poly-Si TFT (LTPS), and his pioneering efforts have greatly contributed to the rapid growth of the mobile display industry. In 2002, he joined Toppoly in Taiwan as Chief Technology Officer. He experienced a two-company merger with Philips Mobile Displays in 2006 as well as the subsequent three-company merger with Innolux and Chimei in 2010. In 2012, he was invited to join Japan Display Inc. to leverage his world-class experiences and expertise in display technologies and business, and serves as Chief Strategy Officer and Deputy Chief Technology Officer. He received SID Fellow Award in 2000, SID Special Recognition Award in 1995, and SID Outstanding Paper Awards in 1985 and 1984. Abstract: Full-color flat panel displays represented by TFT LCD have enabled many new applications such as digital camera, notebook PC and thin flat-screen TV by intensive research activities throughout the world over the years. Recently, small-sized mobile display development has been leading the R&D to support severe requirements of smartphones and tablet PCs. For the screens of those applications, high definition, high visual quality, low power consumption, small form factor and easy-to-use touch user-interface are critical values. The trend shows that even higher pixel density and lower power consumption are required for the future smart devices. In this presentation, mobile display market and the recent technical achievements are reviewed. In addition, expectations on semiconductor technologies for the development of future displays and user-interfaces will be discussed. |
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| Title | Internet of Things: Evolution towards a Hyper-Connected Society | |
| Speaker | Dr. Alex Jinsung Choi | |
| Position | Executive Vice President and Head of ICT R&D Division | |
| Affiliation | SK Telecom | |
| Time/Place | 09:40-10:25 Nov. 11 (Tue), 2014/Diamond II, 41F | |
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Biography: Dr. Alex Jinsung Choi is serving as Executive Vice President and Head of ICT R&D Division of SK Telecom. Dr. Choi joined SK Telecom in 2012 as Senior Vice President and Head of Technology Strategy Office. He is responsible for building the company's technology roadmaps and strategies aimed at securing technology leadership in the rapidly-evolving mobile marketplace. In line with the company's efforts to open a new LTE 2.0 era, his focus is currently on developing next generation network technologies including LTE and LTE-A. Choi has over 20 years of experience in the mobile telecommunications industry. Before joining SK Telecom, he held various key positions at LG Electronics including EVP & Head of Mobile Communications Business Unit, EVP & Head of Mobile Core Technology Lab and SVP & Head of Next-Generation Telecommunications Lab. Choi is credited with developing the world's first LTE handset modem chip and launching LG's first LTE Android smartphone. He has also actively participated in global standardization activities through 3GPP, NGMN, OMA and ITU. He received his Bachelor's degree in Control and Instrumentation Engineering from Seoul National University; and Master's Degree in Computer Engineering and Doctor's degree in Electrical Engineering from University of Southern California. Abstract: IoT(Internet of Things) will encompass all aspects for our lives and will generate a genuine paradigm shift for a hyper-connected society. As more and more little things or objects are connected to the Internet, huge volumes of data are being generated and being processed into useful actions that can make our lives much easier and safer. This creates heavy traffic in existing network systems and therefore causes new challenges for next generation systems. To overcome challenges, IoT systems should be more flexible and scalable to manage and operate than ever before. Cloud computing and big data analytics should be converged into infra. These enable systems to react faster to the needs of service, while driving greater operational efficiency and intelligence. Also, IoT systems must be vertically optimized from Integrated circuits, SoC and devices to network, platform and applications in order to provide extremely low energy consumption, cost-effectiveness, service quality and reliability. That's why IoT is composed of entire technologies including sensing, embedded processing, connectivity and application with highly fragmented markets. Another essential challenge of IoT systems is to guarantee full security and privacy across the entire signal path. Security at the device, network and system levels is paramount for the safe and reliable operation of IoT connected devices. It is, in fact, the foundational enabler of IoT. All these challenges and requirements for IoT systems mean no single company can develop full solutions completely. A broad and rich ecosystem of partner companies will be required to bring IoT services to the market. In this talk, IoT vision and recent R&D challenges of SK telecom as a service provider will be addressed. |
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| Title | Semiconductor Innovation into the Next Decade | |
| Speaker | Dr. Jack Y.-C. Sun | |
| Position | VP R&D and CTO | |
| Affiliation | TSMC | |
| Time/Place | 08:30-09:15 Nov. 12 (Wed), 2014/Diamond II, 41F | |
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Biography: Dr. Sun has been the mastermind behind the success of TSMC logic R&D in providing the most energy-efficient, high-density, high-throughput, and cost-effective CMOS platform and mixed-signal/RF technologies since 0.25um for logic/SOC products and the fabless industry, incl. massive parallel processors like GPU, GP-GPU, and server CPU; high gate-count FPGA; and multi-core (ARM/GPU) application processors for smart phone / mobile computing. He proposed a System Scaling concept and figure of merit, encompassing Si wafer-based CMOS scaling, integrated specialty, and 3D chip stacking technology, to extend "Superchip" and system scaling beyond 2020. Dr. Sun had four IBM invention achievement awards and several IBM Outstanding Technical Accomplishment Awards in the 1990's. He received "Ten Most Outstanding Engineer Award" of the Chinese Institute of Engineers in 2000. He is a co-recipient of "Outstanding Technology Worker Award" from ROC Executive Yuan in 2003 for his leadership and technical contributions in the foundry-leading 0.13um low-power and high performance CMOS technology with world-leading Cu/Low-K interconnects. He won the National Management Excellence Award in 2004. He received 2010 ECE Distinguished Alumni Award from University of Illinois. He also won TSMC Medal of Honor in 2011. Dr. Sun is an IEEE Fellow for his contributions to CMOS technology. He received BSEE degree from National Taiwan University, and MS and Ph.D. degree from the University of Illinois. He has over 200 papers, many invited and plenary talks, 12 US patents, and several ROC patents. Abstract: Mobile computing has been the electronic industry growth driver over the past few years, with monolithic CMOS scaling (Moore's Law) being a key enabler. "Giga-trends", or the "Next Big Thing", such as converged smart devices (i.e.: personal "Command and Control Center") ubiquitously connected to wearables and the internet of things (IoT), with big data and cloud computing as the backbone, will continue to enhance future lifestyles and drive the growth of the silicon-based nano-electronics industry. Going forward, our vision is to realize Energy-Efficient System Scaling that will make systems faster, smaller, lighter, thinner, and consume less power. CMOS scaling (Moore's Law) will continue to be the central pillar of energy-efficient system scaling, with many innovation opportunities and challenges ahead. Two other key system scaling pillars are novel integrated specialty technology and wafer-based 3D chip stacking. CMOS scaling is like the brain, specialty technology like the five senses and human limbs, and 3D chip stacking like the spine of a human body. Through this system scaling approach, the era of silicon-based "super system chips" has arrived. Open and synergistic collaborative innovation is key to technical and business success under the new System Scaling paradigm. TSMC's Grand Alliance and Open Innovation platform (OIP) represent a thriving symbiotic, synergistic, and powerful collaborative ecosystem for the "Next Big Thing" and the continued growth of the silicon-based nano-electronic industry. With its ecosystem partners and suppliers, the TSMC Grand Alliance supports the largest combined R&D investment and innovative power to drive the energy-efficient super system chips that will enrich the future human experience. |
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| Title | Energy Efficient Computing in Nanoscale CMOS: Challenges and Opportunities | |
| Speaker | Dr. Vivek De | |
| Position | Fellow and Director of Circuit Tech. Labs | |
| Affiliation | Intel, USA | |
| Time/Place | 09:20-10:05 Nov. 12 (Wed), 2014/Diamond II, 41F | |
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Biography: Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for providing strategic technical directions for long term research in future circuit technologies and leading energy efficiency research across the hardware stack. He has 220 publications in refereed international conferences and journals and 193 patents, with 30 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He received a PhD in Electrical Engineering from Rensselaer Polytechnic Institute, Troy, New York. He is a Fellow of the IEEE. Abstract: Future computing systems spanning exascale supercomputers to wearable devices demand orders of magnitude improvements in energy efficiency while providing desired performance. The system-on-chip (SoC) designs need to span a wide range of performance and power across diverse platforms and workloads. The designs must achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS process while supporting a wide voltage-frequency operating range with minimal impact on die cost. We will discuss circuit and design technologies to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations. The major pillars of energy-efficient SoC designs are:
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