Supporters & Exhibitors

Important Dates

Aug. 18, 2014
Acceptance notification

Sept. 15, 2014
Deadline for final paper submission
& Author registration deadline

Oct. 31, 2014
Slides due to session chairs

Nov. 9, 2014
Speaker rehearsal

Nov. 10-12, 2014

Local Time (GMT+8)

Taipei, Taiwan

Advanced Program

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2014 IEEE Asia Solid-State Circuits Conference

Advanced Program


DAY 1: Nov. 10 (Monday)
08:30-18:00 Registration (Lobby, 39F)
09:00-10:20 Tutorial 1
Low-voltage Analog and RF Circuits
in Scaled Technologies
Peter Kinget / Columbia University
(Amber+Coral, 42F)
Tutorial 2
Design of On-Chip Switched-Capacitor
Power Converters
Wing-Hung Ki / HKUST
(Agate+Pearl, 42F)
10:20-10:40 Break (drinks/refreshments)
10:40-12:00 Tutorial 2
Design of On-Chip Switched-Capacitor
Power Converters
Wing-Hung Ki / HKUST
(Amber+Coral, 42F)
Tutorial 1
Low-voltage Analog and RF Circuits
in Scaled Technologies
Peter Kinget / Columbia University
(Agate+Pearl, 42F)
12:00-13:00 Break
13:00-14:20 Tutorial 3
Energy efficient digital design – a circuit's perspective
Wim Dehaene / MICAS, KU Leuven & IMEC
(Amber+Coral, 42F)
Tutorial 4
Digital circuits and design techniques for
security and cryptography
Ingrid Verbauwhede / COSIC, KU Leuven & UCLA
(Agate+Pearl, 42F)
14:20-14:40 Break (drinks/refreshments)
14:40-16:00 Tutorial 4
Digital circuits and design techniques for
security and cryptography
Ingrid Verbauwhede / COSIC, KU Leuven & UCLA
(Amber+Coral, 42F)
Tutorial 3
Energy efficient digital design – a circuit's perspective
Wim Dehaene / MICAS, KU Leuven & IMEC
(Agate+Pearl, 42F)
16:00-18:00 SDC Exhibition  (Diamond III, 41F)
19:00-20:30 Welcome Reception  (Diamond II/III, 41F)   SDC Exhibition

Note: Each tutorial lasts 80 minutes and is given twice.

DAY 2: Nov. 11 (Tuesday)
07:45-18:00 Registration (41F)
08:30-08:50 Opening Ceremony (Diamond II, 41F)
08:50-09:35 Session 01: Plenary Talk 1
Mobile Display Technologies  -Past, Present and Future-
Mr. Hiroyuki Ohshima / Japan Display Inc.
(Diamond II, 41F)
09:40-10:25 Session 01: Plenary Talk 2
Internet of Things: Evolution towards a Hyper-Connected Society
Dr. Alex Jinsung Choi / SK Telecom
(Diamond II, 41F)
10:25-10:50 Break (drinks/refreshments, 41F) / SDC Exhibition (Diamond I, 41F)
10:50-12:20 Industry Session 02
Communication Systems
 (Diamond II, 41F)
Industry Session 03
Industrial Digital Subsystems
(Diamond III, 41F)
SDC Exhibition

(Diamond I, 41F)
12:20-13:35 Break
13:35-15:40 Session 04
Energy-efficient Digital
Circuits and Systems
(Diamond II, 41F)
Session 05
DC-DC Converters
(Amber+Coral, 42F)
Session 06
High-speed Data Converters
(Diamond III, 41F)
Session 07
Wireline Transceivers
(Agate+Pearl, 42F)
15:40-16:00 Break (drinks/refreshments, 38F)
16:00-18:00 Session 08: Panel
What is a good way to expand a silicon value to a solution value?

Panelists / Position:
Tzi-Dar Chiueh, National Taiwan University
Toru Shimizu, Keio University
Gregory Chen, Intel
Chen Yi Lee, National Chiao Tung University / Medical and Healthcare
Charles Hsu, eMemory / Security in IoT
Tihao Chiang, Ambarella Taiwan / Video and Surveillance
Zhi-Hwa Wang, Tsinghua University / IoT and Healthcare
Dae Seok Byeon, Samsung Electronics Co. / PC
Jongwoo Lee, Samsung / Mobile
Yasumoto Tomita, Fujitsu Laboratories / Interconnect
Takayuki Kawahara, Tokyo University of Science / Memory System
(Opal Ballroom, 38F)
19:00-21:00 Banquet (Diamond II, 41F)
DAY 3: Nov. 12 (Wednesday)
07:45-18:00 Registration (41F)
08:30-09:15 Session 09: Plenary Talk 3
Semiconductor Innovation into the Next Decade
Dr. Jack Y.-C. Sun / TSMC
(Diamond II, 41F)
09:20-10:05 Session 09: Plenary Talk 4
Energy Efficient Computing in Nanoscale CMOS: Challenges and Opportunities
Dr. Vivek De / Intel
(Diamond II, 41F)
10:05-10:25 Break (drinks/refreshments, 41F)
10:25-12:30 Session 10
Memory Technology
(Agate+Pearl, 42F)
Session 11
Sensor Applications
(Diamond III, 41F)
Session 12
mm-wave and THz
(Amber+Coral, 42F)
Session 13
Biomedical Circuits
and Systems
(Diamond II, 41F)
12:30-13:30 Break
13:30-15:35 Session 14
SoC and Signal Processing Techniques
(Diamond II, 41F)
Session 15
Analog Circuits
and Systems
(Diamond III, 41F)
Session 16
RF Systems
(Amber+Coral, 42F)
Session 17
Equalizer and Clock Data Recovery
(Agate+Pearl, 42F)
15:35-15:55 Break (drinks/refreshments, 41F and 42F)
15:55-18:00 Session 18
Circuit Techniques for Emerging Applications
(Diamond II, 41F)
Session 19
Low Power ADCs
(Diamond III, 41F)
Session 20
RF Building Blocks
(Amber+Coral, 42F)
Session 21
High-speed Wireline Building Blocks
(Agate+Pearl, 42F)
18:00-19:30 Farewell Social Hour (Diamond I, 41F)



Day 1     Monday, November 10, 2014


[Tutorial 1]

TITLE                                   Low-voltage Analog and RF Circuits in Scaled Technologies          

DATE / TIME                       November 10, 2014 (Monday) / 09:00-12:00 hrs

ROOM                                  Amber+Coral, 42F (09:00-10:20)

                                             Agate+Pearl, 42F (10:40-12:00)

SPEAKER                             Peter Kinget, Columbia University


Peter Kinget is a Professor of Electrical Engineering at Columbia University, NY. He is also a consulting expert on patent litigation and a technical consultant to industry. His research interests are in analog, RF and power integrated circuits and the applications they enable in communications, sensing, and power manage-ment. He is a fellow of the IEEE, is widely published and received several awards. He has been a "Distinguished Lecturer" for the Solid-State Circuits Society, and an Associate Editor of the Journal of Solid State Circuits and the Transactions on Circuits and Systems II. He has served on the program committees of many of the major solid-state circuits conferences and is currently an elected member of the IEEE SSCS Adcom.


Abstract: CMOS technology scaling has fueled tremendous progress in electronics and has enabled system-on-chip (SoC) products. Scaling increases the performance and density for digital signal processing, computation and memory. But, analog and RF circuits remain the critical interfaces to connect the digital cores of SoCs to the physical world and need to satisfy increasing performance demands. At the same time, designing analog and RF functions with sub-1V supply voltages in scaled processes is very challenging.

This tutorial will start with reviewing the basic analog and RF low voltage challenges and how they force a rethinking of even the most basic circuit blocks. We will review design solutions to operate analog and RF circuits with supply voltages down to 0.5V. They range from exploiting the 4 terminals of the MOS device, to the use of circuit topologies that require only stacks of few devices, to the complete reengineering of the circuit architecture or even the use of different analog information representations. They will be illustrated with design examples of full analog and RF system functions.


[Tutorial 2]

TITLE                                   Design of On-Chip Switched-Capacitor Power Converters             

DATE / TIME                       November 10, 2014 (Monday) / 09:00-12:00 hrs

ROOM                                  Agate+Pearl, 42F (09:00-10:20)

                                             Amber+Coral, 42F (10:40-12:00)

SPEAKER                             Wing-Hung Ki, HKUST


Wing-Hung Ki received his BSc from University of California, San Diego (UCSD, 1984), MSc from California Institute of Technology (Caltech, 1985), and PhD from University of California, Los Angeles (UCLA, 1995), all in electrical engineering. From 1992 to 1995, he worked for Micro Linear, San Jose, on the design of power converter controllers. He joined the Hong Kong University of Science and Technology (HKUST) in 1995, and is currently a professor of the Department of Electronic and Computer Engineering. His research interests are IC techniques for power management circuits, power transponders for RFID and energy harvesting applications, and fundamental research in switching converters, charge pumps and analog IC techniques.

Abstract: With the increasing demand of integrating voltage regulators completely on-chip, switched-capacitor power converters that consist of only capacitors and switches are gaining popularity as substitutes for inductor-based DC-DC converters. Switched-capacitor power converters (SCPCs) are often known as charge pumps, especially for those with voltage conversion ratios larger than unity.


This tutorial starts with classifications of charge pumps. Charge balance law is then introduced, and charge redistribution loss is discussed. Topologies of step-up charge pumps are generated systematically using the ANTZ (all negative nodes to zero) principle, and efficiency optimization is presented. Gate control techniques, loss reduction considerations, single-branch, dual-branch and multi-phase implementations and step-down charge pumps will also be discussed.


[Tutorial 3]

TITLE                                   Energy Efficient Digital Design – a Circuit's Perspective   

DATE / TIME                       November 10, 2014 (Monday) / 13:00-16:00 hrs

ROOM                                  Amber+Coral, 42F (13:00-14:20)

                                             Agate+Pearl, 42F (14:40-16:00)

SPEAKER                             WimDehaene, MICAS, KU Leuven & IMEC


WimDehaene received the M. Sc. degree in electrical and mechanical engineering in 1991 from the KatholiekeUniversiteit Leuven. In November 1996 he received the Ph. D degree at the KatholiekeUniversiteit Leuven. In November 1996 he joined Alcatel Microelectronics, Belgium. There he was a senior project leader for the feasibility, design and development of mixed mode Systems on Chip. The application domains were telephony, xDSL and high speed wireless LAN. In July 2002 WimDehaene joined the staff of the ESAT-MICAS laboratory of the KatholiekeUniversiteit Leuven where he is now a full professor. His research domain is circuit level design of digital circuits. The current focus is on ultra low power signal processing and memories in advanced CMOS technologies. Part of this research is performed in cooperation with IMEC, Belgium where he is also a part time principal scientist. WimDehaene is teaching several classes on electrical engineering and digital circuit and system design. He is also very interested in the didactics of engineering. As such he is guiding several projects aiming to bring engineering to youngsters and he is a teacher in the teacher education program of the KULeuven. WimDehaene is a senior member of the IEEE and served on the technical program committee of DATE, ESSCIRC and ISSCC.


Abstract: In this tutorial the design of energy efficient digital circuit design will be addressed. The focus will be on transistor and gate level and eventually microarchitecture. The tutorial will start by introducing the problem: where does the energy go in digital circuits and why is energy efficiency even more of an issue as the CMOS technology becomes more advanced. This will put static leakage and device variability on the map. From there on several techniques to improve the energy efficiency will be explained. Both dynamic and static energy (leakage) will be dealt with. It will be shown that design strategies for energy efficiency are different for logic and memory design. Therefore design examples from both domains will be illustrated.


[Tutorial 4]

TITLE                                   Digital Circuits and Design Techniques for Security and Cryptography

DATE / TIME                       November 10, 2014 (Monday) / 13:00-16:00 hrs

ROOM                                  Agate+Pearl, 42F (13:00-14:20)

                                             Amber+Coral, 42F (14:40-16:00)

SPEAKER                             Ingrid Verbauwhede, COSIC, KU Leuven  & UCLA

Ingrid Verbauwhedeis a Professor in the research group COSIC of the EE Department of the KU Leuven in Belgium. At COSIC, she leads the embedded systems and hardware group. She is also adjunct professor at the EE department at UCLA, Los Angeles, CA. She has experience as a post-doctoral researcher and lecturer at UC Berkeley and she worked for TCSI and Atmel in Berkeley, CA. She received her MSc and PhD degree from KU Leuven in 1991. She is a Member of IACR and the Belgian Academy of Science and she is a fellow of IEEE. Her main interest is in the design and the design methods for secure embedded circuits and systems.  Her list of publications and patents is available at


Abstract: E-Health, e-commerce, smart meters, cyber physical systems, and many more, all need secure and efficient implementations of cryptography for their correct and trusted operation.


Implementing cryptographic algorithms into embedded devices, is a challenge for efficiency reasons as well as security reasons. Because the algorithms use unusual arithmetic, are computationally intensive and often use very large word lengths, it is difficult to fit them into the area, throughput,  power and/or energy constraints. Moreover, the implementations have to be made resistant to a wide range of physical attacks, both invasive and non-invasive. Thus adding countermeasures to the implementations, adds an extra optimization goal. In this tutorial, implementations for efficiency as well as security of cryptographic algorithms will be covered.


[Student Design Contest]

DATE / TIME                     November 10, 2014 (Monday) / 16:00-20:30 hrs


ROOM                                 Diamond III, 41F



Day 2     Tuesday, November 11, 2014


Opening Ceremony

DATE / TIME                     November 11, 2014 (Monday) / 08:30-08:50 hrs

ROOM                                 Diamond II, 41F


Session                               01: Plenary

Date / Time                       November 11, 2014 (Tuesday) / 08:50-10:25 hrs

Venue                                 Diamond II, 41F


[Plenary Talk 1]

TITLE                                   Mobile Display Technologies – Past, Present, and Future

DATE / TIME                       November 11, 2014 (Tuesday) / 08:50-09:35hrs

SPEAKER                             Hiroyuki Ohshima, CSO/Deputy CTO, Japan Display Inc.


Mr. Ohshima completed his BS degree from Tokyo University in 1979, and joined Seiko Epson.  He has been engaged in TFT LCD technologies and the FPD industry for more than 30 years.  In 1983, he developed high-temperature poly-Si TFT (HTPS) and applied it to the world's first color TFT LCD.  It was his first achievement in his TFT history, and was presented at SID in 1983.  Later, he redirected his R&D efforts towards development of low-temperature poly-Si TFT (LTPS), and his pioneering efforts have greatly contributed to the rapid growth of the mobile display industry.

In 2002, he joined Toppoly in Taiwan as Chief Technology Officer.  He experienced a two-company merger with Philips Mobile Displays in 2006 as well as the subsequent three-company merger with Innolux and Chimei in 2010.


In 2012, he was invited to join Japan Display Inc. to leverage his world-class experiences and expertise in display technologies and business, and serves as Chief Strategy Officer and Deputy Chief Technology Officer.


He received SID Fellow Award in 2000, SID Special Recognition Award in 1995, and SID Outstanding Paper Awards in 1985 and 1984.


Abstract: Full-color flat panel displays represented by TFT LCD have enabled many new applications such as digital camera, notebook PC and thin flat-screen TV by intensive research activities throughout the world over the years. Recently, small-sized mobile display development has been leading the R&D to support severe requirements of smartphones and tablet PCs. For the screens of those applications, high definition, high visual quality, low power consumption, small form factor and easy-to-use touch user-interface are critical values. The trend shows that even higher pixel density and lower power consumption are required for the future smart devices. In this presentation, mobile display market and the recent technical achievements are reviewed. In addition, expectations on semiconductor technologies for the development of future displays and user-interfaces will be discussed.


[Plenary Talk 2]

TITLE                                   Internet of Things: Evolution towards a Hyper-Connected Society

DATE / TIME                       November 11, 2014 (Tuesday) / 09:40-10:25 hrs

SPEAKER                             Alex Jinsung Choi, SK Telecom, South Korea

Dr. Alex Jinsung Choi is serving as Executive Vice President and Head of ICT R&D Division of SK Telecom. Dr. Choi joined SK Telecom in 2012 as Senior Vice President and Head of Technology Strategy Office. He is responsible for building the company's technology roadmaps and strategies aimed at securing technology leadership in the rapidly-evolving mobile marketplace. In line with the company's efforts to open a new LTE 2.0 era, his focus is currently on developing next generation network technologies including  LTE and LTE-A. 


Choi has over 20 years of experience in the mobile telecommunications industry. Before joining SK Telecom, he held various key positions at LG Electronics including EVP & Head of Mobile Communications Business Unit, EVP & Head of Mobile Core Technology Lab and SVP & Head of Next-Generation Telecommunications Lab. Choi is credited with developing the world's first LTE handset modem chip and launching LG's first LTE Android smartphone. He has also actively participated in global standardization activities through 3GPP, NGMN, OMA and ITU.

He received his Bachelor's degree in Control and Instrumentation Engineering from Seoul National University; and Master's Degree in Computer Engineering and Doctor's degree in Electrical Engineering from University of Southern California.


Abstract: IoT(Internet of Things) will encompass all aspects for our lives and will generate a genuine paradigm shift for a hyper-connected society. As more and more little things or objects are connected to the Internet, huge volumes of data are being generated and being processed into useful actions that can make our lives much easier and safer. This creates heavy traffic in existing network systems and therefore causes new challenges for next generation systems. To overcome challenges, IoT systems should be more flexible and scalable to manage and operate than ever before. Cloud computing and big data analytics should be converged into infra. These enable systems to react faster to the needs of service, while driving greater operational efficiency and intelligence. Also, IoT systems must be vertically optimized from Integrated circuits, SoC and devices to network, platform and applications in order to provide extremely low energy consumption, cost-effectiveness, service quality and reliability. That's why IoT is composed of entire technologies including sensing, embedded processing, connectivity and application with highly fragmented markets. Another essential challenge of IoT systems is to guarantee full security and privacy across the entire signal path. Security at the device, network and system levels is paramount for the safe and reliable operation of IoT connected devices. It is, in fact, the foundational enabler of IoT. All these challenges and requirements for IoT systems mean no single company can develop full solutions completely. A broad and rich ecosystem of partner companies will be required to bring IoT services to the market. In this talk, IoT vision and recent R&D challenges of SK telecom as a service provider will be addressed.


Session                               02: Communication Systems

Date / Time                       November 11, 2014 (Tuesdsay) / 10:50-12:20hrs

Venue                                 Diamond II, 41F

Chair                                   ShiroDosho, Panasonic, Japan

Co-Chair                             Hsiang-Hui Chang, MediaTek, Taiwan




A Reconfigurable Analog Baseband for Single-Chip, Saw-Less, 2G/3G/4G Cellular Transceivers with Carrier Aggregation

Jongwoo Lee, Byungki Han, Jae-Hyun Lim, Su-SeobAhn, Jaekwon Kim, Thomas Cho

Samsung Electronics, South Korea.


This paper describes an analog baseband for single-chip 2G/3G/4G MIMO transceivers. By capacitor sharing technique and log tuning, the RX filter is programmable to set fc from 0.1 to 14MHz with 2% accuracy with 93dB gain range which is linear-in-dB. The TX filter suppresses DAC images and noise for Saw-less with constant or ramping envelope. A digital calibration adjusts fc, Q, and DC offset. The filter implemented in 65nm CMOS, occupies 2.79mm2, and consumes 7.3/8.4/10.2mW with 1.2V supply for 2G/3G/4G, respectively. This chip is in mass production for handheld products.


Keywords: CMOS analog filter, logarithmic tuning resistor




A Low-Power Single-Chip Transceiver for 169/300/400/900 MHz Band Wireless Sensor Networks

Makoto Oba, Eiji Okada, Ayako Tachibana, Koji Takahashi, Masahiko Sagisaka

Panasonic Corporation, Japan.


A low-power transceiver for wireless sensor networks at sub-GHz frequency bands is presented, which integrates an RF frontend as well as a digital baseband and a MAC layer into a single 3.0 mm2 chip. The transceiver covers 169/300/400/900 MHz bands and supports FSK/GFSK modulation with a data rate from 1.2 to 200 kbps. A prototype is fabricated in 65 nm CMOS, achieving only 8.2 mA in the RX and 23 mA in the TX with +10 dBm output power at 915 MHz from a 3.3 V supply.


Keywords: Low-Power, Single-Chip, Wireless Sensor Networks, Active Inductor, Harmonic-Rejection




A 1.4Mpixel CMOS Image Sensor with Multiple Row-Rescan Based Data Sampling for Optical Camera Communication

Jun Deguchi, Toshiyuki Yamagishi, Hideaki Majima, Nau Ozaki, Kazuhiro Hiwada, Makoto Morimoto, TatsujiAshitani, ShouheiKousai

Toshiba Corporation, Japan.


A 1.4Mpixel CMOS image sensor (CIS) with multiple row-rescan (MRR) based data sampling for optical camera communication (OCC) is presented.  The CIS achieves a data sampling rate at a row-scan rate of 51kS/s even with a frame rate of 30fps, a pixel size of 2.2um × 2.2um by multiply rescanning the rows at a modulated LED spot.  The detectable minimum LED size projected onto the CIS becomes 13.2um × 13.2um.  The MRR could be a practical solution for IEEE 802.15.SG7a OCC.


Keywords: IEEE 802.15.7 VLC, IEEE 802.15.SG7a OCC, CMOS image sensor, multiple row-rescan


Session                               03: Industrial Digital Subsystems

Date / Time                       November 11, 2014 (Tuesday) / 10:50-12:20hrs

Venue                                 Diamond III, 41F

Chair                                   Daisaburo Takashima, Toshiba, Japan

Co-Chair                             Ron Ho, Altera, USA




A 2.4 pJ Ferroelectric-Based Non-Volatile Flip-Flop with 10-Year Data Retention Capability

Hiromitsu Kimura2, Takaaki Fuchikami2, Kyoji Marumoto2, Yoshikazu Fujimori2, Shintaro Izumi1, Hiroshi Kawaguchi1, Masahiko Yoshimoto1

1Kobe University, Japan.

2ROHM Co., Ltd., Japan.


A ferroelectric-based (FE-based) non-volatile flip-flop (NVFF) is proposed for low-power LSI. Since leakage current in a logic circuit can be cut off by non-volatile storage capability of NVFFs, the standby power is reduced to zero. The use of complementarily stored data in coupled FE capacitors makes it possible to achieve 88% reduction of FE capacitor size with a wide voltage margin of 240mV (minimum) at 1.5V, which results in 2.4pJ low access energy with 10-year data retention capability. Applying the proposed circuitry in 32bit CPU, its power consumption becomes 13% of that of conventional one with area overhead of 64% using 130nm CMOS with Pb(Zr,Ti)O3 (PZT) thin films.


Keywords: Non-volatile logic, Non-volatile flip-flop, Ferroelectric capacitor, Low power, Microporcessor




40 nm Dual-Port and Two-Port SRAMs for Automotive MCU Applications Under -40 to 170øC Wide Temperature Range with Test Screening Circuit Against Write Disturb Issue

Yoshisato Yokoyama1, Yuichiro Ishii1, Koji Tanaka1, Tatsuya Fukuda1, Yoshiki Tsujihashi1, Astushi Miyanishi1, Shinobu Asayama2, Keiichi Maekawa2, Kazutoshi Shiba2, Koji Nii1

1Renesas Electronics, Japan.

2Renesas Semiconductor Manufacturing, Japan.


A 2-read/write dual-port SRAM and 1-read/1-write two-port SRAM with stable operation under widely various temperatures of -40 to 170øC are implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. To reduce the leakage current and ensure the read/write operating margin at over 125C, process and sizing optimized new 8T SRAM bitcell with is proposed. A test circuits for screening the disturb failures for dual-port and two-port SRAM s are also proposed. Designed and fabricated test chips showed the measured Vmin are achieved under 0.7 V with good distribution. We confirmed the proposed test circuits can screen the disturb failures effectively.


Keywords: SRAM, MCU, 40 nm, 170øC, disturb, 8T, dual-port, two-port, memory, screening, testability




A UHS-II SD Card Controller with 240MB/S Write Throughput and 260MB/S Read Throughput

Kenta Yasufuku1, Naoto Oshiyama1, Toshitada Saito1, Yukimasa Miyamoto1, Yutaka Nakamura1, Ryota Terauchi1, Atsushi Kondo1, Takuma Aoyama1, Masafumi Takahashi1, Yukihito Oowaki1, Ryoichi Bandai2

1Toshiba Corporation, Japan.

2Toshiba Microelectronics Corporation, Japan.


This paper presents a UHS-II SD card controller with 240MB/s write and 260MB/s read throughput. Two opposite direction IO lanes for down- and up-streams are quickly switched as single direction for double data rate, without adding extra IO pins. The proposed clock data recovery (CDR) logic can detect symbols within 20ns and minimizes this lane switching overhead. The developed SLVS-type driver that can reduce the common to differential return loss by 15dB is also introduced to improve the noise tolerance.


Keywords: SD cards, UHS-II, serial interface, bidirectional, CDR, return loss


Session                               04: Energy-efficient Digital Circuits & Systems

Date / Time                       November 11, 2014 (Tuesday) / 13:35-15:40hrs

Venue                                 Diamond II, 41F

Chair                                   Keiichi Kushida, Toshiba, Japan

Co-Chair                             Tai-Jyi Lin, Chung Cheng University, Taiwan




A 0.43pJ/Bit True Random Number Generator

Ting-KueiKuan, Yu-Hsuan Chiang, Shen-Iuan Liu

National Taiwan University, Taiwan.


A small-area energy-efficient true random number generator (TRNG) is presented. This TRNG introduces a jitter signal generator to realize the noise pre-amplification, and utilizes a metastable latch to resolve the jitter edges. Moreover, to tolerate the process and environment variations, an offset calibration is employed to dynamically correct the bias of the probability of logic 0/1 in background. A prototype is fabricated in 40-nm CMOS technology. It occupies an area of 0.0014mm2 and consumes 214nW from a 0.8-V supply at a throughput of 500kbps. The proposed TRNG passes the NIST tests, and its calculated FOM is 0.43pJ/bit.


Keywords: True Random Number Generator, TRNG, Background Calibration, Process Tolerance, Environment Variation, Energy-Efficient, Small-Area, RFID




A 4.5 to 13 Times Energy-Efficient Embedded Microprocessor with Mainly-Static/Partially-Dynamic Reconfigurable Array Accelerator

ItaruHida, Dahoo Kim, Tetsuya Asai, Masato Motomura

Hokkaido University, Japan.


Conventional processors are energy in-efficient in that they fail to utilize the fact that most of their time and energy are spent on heavily-recursively executed small code segments. A DYNaSTA accelerator, proposed and implemented, is an architectural solution to such a problem. It is an reconfigurable array accelerator featuring an hybrid architecture: only a limited portion is reconfigured dynamically while the rest is reconfigured statically. This way, the DYNaSTA accelerator tries to achieve both flexibility and energy-efficiency at the same time. Results of power simulation and fabricated chip measurements have been quite encouraging: 4.5 to 13 times energy efficiency will be made possible by this accelerator when compared with a conventional embedded microprocessor.


Keywords: EMP, ASIC, energy efficiency, reconfigurable system




A Sub-Threshold to Super-Threshold Level Conversion Flip Flop for Sub/Near-Threshold Dual-Supply Operation

Chao Wang2, Jun Zhou2, Xin Liu2, Arasu Annamalai2, Minkyu Je1

1Daegu Gyeongbuk Institute of Science & Technology, South Korea.

2Institute of Microelectronics, Singapore, Singapore.


this paper presents a novel Current-Mirror (CM) based Master-Slave Level Conversion Flip Flop (MS-LCFF) to perform data latching and level shifting from sub-threshold voltage, to near-threshold voltage, and up to super-threshold voltage. The CM-based MS-LCFF enables energy-efficient ultra-low-voltage operation by applying dual-supply and multi-supply designs into sub/near-threshold regions. Simulation results show that with a 0.18-μm technology the proposed LCFF is able to conduct data latching and level shifting from 0.3 V to 0.5 V, and up to 1.8 V, with performance improved by 8×, power consumption decreased by 3×, and silicon area reduced by 13.3% over the conventional method, when performing conversion from 0.3 V to 0.5 V. The measurement results of applying the proposed LCFF-based dual-supply operation to a sub-threshold FIR filter operating at 300 kHz demonstrate that a 21.8% power reduction can be achieved without performance loss by dual-supply operation at 0.3V and 0.5V, compared to the single-supply operation at 0.5V.


Keywords: level conversion flip flop, dual-supply operation, sub/near-threshold operation, ultra low voltage digital circuit, energy efficiency




Wide-Supply-Range All-Digital Leakage Variation Sensor for on-Chip Process and Temperature Monitoring

A.K.M. Mahfuzul Islam, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

Kyoto University, Japan.


Variation in process, voltage and temperature is a major obstacle in achieving energy-efficient operation of LSI. This paper proposes an all-digital on-chip circuit to monitor leak- age current variations of both of the nMOSFET and pMOSFET independently. As leakage current is highly sensitive to threshold voltage and temperature, the circuit is suitable for tracking process and temperature as well. An estimation method of threshold voltage variation from the monitored leakage variation is developed. The circuit uses reconfigurable inhomogeneity to obtain statistical properties from a single monitor instance. Cell- base design approach is taken so that design cost is minimized. Measurement results from a 65-nm test chip shows the validity of the proposed circuit. Total area is 4500 μm2 and active power consumption is 50 nW at 1.0 V operation. The proposed technique enables area-efficient and low-cost implementation thus can be used in product chips for applications such as testing and post- silicon tuning.


Keywords: Leakage Current, Process Variation, On-chip Monitor, Digital, Temperature




Ultra-Low Voltage Datapath Blocks in 28nm UTBB FD-SOI

Hans Reyserhove, NeleReynders, WimDehaene

KULeuven, Belgium.


This paper demonstrates a wide supply range multiply-accumulate datapath block in 28nm UTBB FD-SOI technology. Variability and leakage reduction strategies are employed in this new technology to achieve a state-of-the-art low energy performance. The design uses a wide range of supply voltages to reduce energy consumption per operation. The extensive back-gate biasing range allows to adapt the minimum energy point (MEP) of the circuit to the desired workload. Measurements showcase the speed/energy trade-off of both the design and the technology and lead to a MEP of 0.17pJ at 35MHz with a supply voltage of 250mV and a back-gate bias of 0.5V.


Keywords: Sub-threshold, Near-threshold, Silicon-On-Insulator, 28nm UTBB FD-SOI, Low Voltage, Low Energy, Low Power, Minimum Energy Operation, Datapath




A Body Bias Generator with Wide Supply-Range Down to Threshold Voltage for Within-Die Variability Compensation

NorihiroKamae, A.K.M. Mahfuzul Islam, Akira Tsuchiya, Hidetoshi Onodera

Kyoto University, Japan.


A body bias generator (BBG) for fine-grain body biasing (FGBB) that can operate under wide supply-range is proposed. This paper proposes a BBG that generates forward and reverse body bias only from a core supply voltage ranging from the near threshold of 500mV to the nonminal voltage of 1.2V . This wide operating range is achieved by a low voltage error amplifier with a Vth biasing scheme achieved by internal switched-capacitor charge pumping. We fabricated the forward/reverse BBG in a 65nm CMOS process to control 0.22mm^2 of core circuit with the area overhead of 2.3%.


Keywords: body bias generator, low voltage, wide supply voltage, DVFS, design automation, substrate island


Session                               05: DC-DC Converters

Date / Time                       November 11, 2014 (Tuesday) / 13:35-15:40hrs

Venue                                 Amber+Coral, 42F

Chair                                   Yasuhiro Sugimoto, Chuo University, Japan

Co-Chair                             Sai-Weng Sin, University of Macau, Macau




A Monolithic Capacitor-Current-Controlled Hysteretic Buck Converter with Transient-Optimized Feedback Circuit

Shih-HsiungChien, Ting-Hsuan Hung, Szu-Yu Huang, Tai-HaurKuo

National Cheng Kung University, Taiwan.


This paper proposes a monolithic capacitor-current-controlled hysteretic buck converter with a transient-optimized feedback circuit (TOFC) and a transient-hold (TH) technique. The proposed TOFC simultaneously optimizes both load and dynamic voltage scaling (DVS) transient responses. In addition, the proposed TH technique significantly reduces the required compensation capacitance to save chip area. Implemented in a 0.35-μm CMOS process, this work occupies 0.88 mm2. Measured results show that, for 500-mA step-up load current, output voltage is settled within 0.9 μs, and for 0.6-V DVS, output voltage is settled within 3 μs. Peak efficiency of 96% is measured at 500 mW output power.


Keywords: DC-DC buck converter, capacitor-current sensor, dynamic voltage scaling, DVS, fast transient response




An 83% Peak Efficiency and 1.07W/mm2 Power Density Single Inductor 4-Output DC-DC Converter with Bang-Bang Zeroth-Order Control

Dongchul Park, Tea-Hwang Kong, Gyu-Hyeong Cho

KAIST, South Korea.


This paper presents a new control scheme dubbed Bang-Bang Zeroth-Order Control (BBZOC) for Single Inductor Multiple Output (SIMO) buck converter. The main loop control utilizes a phase detector, charge pump, filter, and comparator. The SIMO buck converter with BBZOC simplifies the compensation design compared to conventional voltage mode control. This work is fabricated in 1P4M 0.35um BCD process and achieves 83% maximum efficiency with the rated output power of 1.04W. The maximum output power is 2.7W and the maximum power density is 1.07 W/mm2. Considering the difference in the process, this work represents the state of the art in the power density.


Keywords: Single Inductor Multiple Ouput, SIMO, Zero-Order Control, Bang-Bang, Comparator, Freewhreeling, DC-DC Converter, Efficiency, Power Density, Filter




CCM/GM Relative Skip Energy Control in Single-Inductor Multiple-Output DC-DC Converter for Wearable Decive Power Solution

Ke-Horng Chen

EE, National Chiao Tung University, Taiwan.


Compact size wearable devices require multiple supplies with relative large loading difference, which causes serious cross regulation, large ripple and oscillation in single-inductor multiple-output (SIMO) DC-DC converter. Thus, a continuous conduction mode/green mode (CCM/GM) relative skip energy control (RSEC) in single-inductor multiple-output (SIMO) is proposed for wearable device power solution. Different from conventional absolute skip method, the RSEC eliminates unnecessary skip-induced voltage ripple and cross regulation with well regulation performance over wide load and voltage ranges. Optimization between efficiency and voltage ripple achieves low noise supply and reduced switching loss. Moreover, smooth transition between CCM and GM provides high power and longer usage time in wearable devices. The test chip fabricated in 0.18μm CMOS process occupies 2.24mm2 active area. Maximum output ripple, overshoot/undershoot and cross regulation are kept below 17mV, 27mV and 0.0432mV/mA, respectively.


Keywords: single-inductor multiple-output, absolute skip, relative skip energy control, continuous conduction mode, green mode




A Current-Mode Buck Converter with Bandwidth Reconfigurable for Enhanced Efficiency and Improved Load Transient Response

Pai-Yi Wang1, Li-Te Wu2, Tai-Haur Kuo1

1National Cheng Kung University, Taiwan.

2NeoEnergy Microelectronics, Inc., Taiwan.


Current-mode control is commonly used in buck converters. Many current-mode buck converters with variable-frequency controllers have been published for smaller inductance and maintaining efficiency via fast and slow frequency, respectively. However, bandwidth of the current-mode buck converter with fixed compensation coefficients is limited by the lowest switching frequency, thus decreases transient speed. This paper proposes a current-mode buck converter with reconfigurable compensation coefficients controlled by a switched-capacitor compensator and activated by a transient detector. Fabricated in 0.35μm CMOS process, this chip occupying 0.91mm2 achieves 96.3% peak efficiency. A 5μs settling time is measured with 75mV undershoot for 700mA load transition.


Keywords: current mode, dc-dc converter, switched capacitor, compensator, transient response




A 20MS/S Buck/Boost Supply Modulator for Envelope Tracking Applications with Direct Digital Interface

Ke-Horng Chen

EE, National Chiao Tung University, Taiwan.


a buck/boost supply modulator (BBSM) is proposed for 4G LTE RF power amplifier (RF-PA) envelope tracking applications. The H-bridges used in non-inverting buck/boost converters are metamorphosed into the current sources and switches of a 4-bit current-steering DAC-like supply modulator. Fast tracking speed is achieved through its inherent open-loop topology, while the direct digital interface provides easy control and integration with digital LTE baseband Socs. The proposed BBSM is capable of delivering peak power of 2.8W at 20MS/s, with a peak efficiency of 75 %.


Keywords: Supply modulator, envelope tracking, non-inverting buck/boost converter.


Session                               06: High Speed Data Converters

Date / Time                       November 11, 2014 (Tuesday) / 13:35-15:40hrs

Venue                                 Diamond III, 41F

Chair                                   Tsung-Heng Tsai, National Chung-Cheng University, Taiwan

Co-Chair                             Takeshi Yoshida, Hiroshima University, Japan




A 10-Bit 320-Ms/S Low-Cost SAR ADC for IEEE 802.11ac Applications in 20-nm CMOS

Chun-Cheng Liu

MediaTek Inc., Taiwan.


This paper presents a low-cost SAR ADC design for IEEE 802.11ac applications. A binary-scaled recombination weighting method for SAR ADC is disclosed in this work. The proposed SAR ADC achieved 9.29 ENOB with an FOM of 6.8 fJ/conversion-step at 0.9 V and 160 MS/s, and achieved 9.20 ENOB with an FOM of 8.1 fJ/conversion-step at 1.0 V and 320 MS/s. This ADC core only occupies an area of 33 um × 35 um in 20-nm CMOS process.


Keywords: SAR ADC, IEEE 802.11ac, 20nm CMOS




A 0.6V 6.4fJ/Conversion-Step 10-Bit 150MS/S Subranging SAR ADC in 40nm CMOS

Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen, Hsin-Shu Chen

National Taiwan University, Taiwan.


A 0.6V 10-bit 150MS/s single-channel asynchronous subranging SAR ADC using a settling-time relief technique is presented. The technique extends the allocated DAC settling time with the assistance of a coarse ADC and minimizes digital loop delay so that it can reach high speed and low power at a 0.6V supply. This ADC consumes 0.264mW at 150MS/s and achieves a peak SNDR of 55.75dB in 40nm CMOS technology. It results in anFoM of 3.5fJ/c.-s. Due to no extra calibration circuit, the core circuit only occupies an area of 0.0063 mm^2.


Keywords: Analog to digital converter (ADC), successive approximation register (SAR), subranging, settling time.




A 0.5-to-1 V 9-Bit 15-to-90 Ms/S Digitally Interpolated Pipelined-SAR ADC Using Dynamic Amplifier

James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa

Tokyo Institute of Technology, Japan.


This paper presents a 0.5-to-1 V, 9-bit, 15-to-90 MS/s digitally interpolated pipelined-SAR ADC. The proposed digital interpolation alleviates the inter-stage gain requirement of a pipelined-SAR ADC making this ADC insensitive to gain variation. With a relaxed gain requirement, an open-loop dynamic amplifier is employed as the residue amplifier making the proposed design high-speed, clock-scalable, and robust to supply voltage scaling. The prototype ADC fabricated in 65 nm CMOS demonstrates an ENOB of 7.88 bits up to 30 MS/s with an input close to the Nyquist frequency at 0.6 V. At this conversion rate, it consumes 0.48 mW resulting in a FoM of 68 fJ/conv.-step.


Keywords: Analog-to-Digital Converter, Digital Interpolation, Dynamic Amplifier, Pipelined-SAR ADC, Ultra-Low-Voltage




A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

Lukas Kull2, Jan Pliva3, Thomas Toifl2, Martin Schmatz2, Pier Andrea Francese2, Christian Menolfi2, Matthias Braendli2, Marcel Kossel2, Thomas Morf2, Toke Andersen2, Yusuf Leblebici1

1EPFL, Switzerland.

2IBM Research - Zurich, Switzerland.

3TU Dresden, Germany.


An area- and power-optimized asynchronous 32x interleaved SAR ADC achieving 36 GS/s at 110mW with 1V supply on the interleaver and 0.9V on the SAR ADCs is presented. The ADC features a 2-channel interleaver with data demultiplexing for enhanced bandwidth, a power- and areaoptimized binary SAR ADC, and an area-optimized clocked reference buffer with a tunable constant-current source. It achieves 32.6 dB SNDR up to 3 GHz and 31.6 dB up to 18 GHz input frequency and 98 fJ/conversion-step with a core chip area of 340x140 μm2 in 32nm SOI CMOS technology.


Keywords: SAR, ADC, SOI, CMOS, 802.3bj, analog-to-digital converter, successive approximation, reference buffer




A 12 Bit 250 Ms/S 28 mW +70 dB SFDR DAC in 0.11 μm CMOS Using Controllable RZ Window for Wireless SoC Integration

Seonggeon Kim, Jaehyun Kang, Minjae Lee

GIST, South Korea.


A 12bit CMOS current-steering digital-to-analog converter (DAC) in 0.11 μm CMOS technology is presented for IQ baseband wireless transmitter and envelop tracking (ET) power amplifier that requires low power consumption with the flexible swing and common-mode controls. The conventional half clock period return-to-zero (RZ) effectively eliminates code-dependent transient but results in amplitude loss. The proposed controllable RZ window less than 50 % of clock duty cycle mitigates such signal loss, and yet achieves the spurious-free dynamic range (SFDR) better than 70 dB up to Nyquist bandwidth at the sample frequency of 250 MHz.  The core area of the DAC is 0.117 mm2 and it dissipates about 28 mW under 2.5 V supply.


Keywords: Current-steering, digital-to-analog converter (DAC), return-to-zero (RZ), cascode, dynamic element matching (DEM), spurious-free dynamic range (SFDR)


Session                               07: Wireline Transceivers

Date / Time                       November 11, 2014 (Tuesday) / 13:35-15:40hrs

Venue                                 Agate+Pearl, 42F

Chair                                   Jung-Hoon Chun, Sungkyunkwan University, Korea

Co-Chair                             Yoshiyuki Ota, Renesas, Japan




A 2 X 20-Gb/S, 1.2-pJ/Bit, Time-Interleaved Optical Receiver in 40-nm CMOS

Shih-Hao Huang, Wei-Zen Chen

Institute of Electronics, National Chiao-Tung University, Taiwan.


This paper describes a single chip, 2 x 20-Gb/s time-interleaved integrating-type optical receiver. Combining with correlation-based timing recovery and 1:4 demultiplexer, it achieves a high energy efficiency of 1.2-pJ/bit. By incorporating the proposed alternating photodetector (ALPD) current-sensing scheme, the front-end receiver is 4-way time-interleaved to increase input sensitivity and relax operating speed of digital comparator. The optical receiver achieves an input sensitivity of 44 μApp at bit-error-rate of less than 1E-12. Fabricated in a 40-nm bulk CMOS technology, the chip size is 0.46 square mm.


Keywords: Monolithic optical receiver, high-density optical interconnect, photodetector (PD), comparator




A 26.5 Gb/S Optical Receiver with All-Digital Clock and Data Recovery in 65nm CMOS Process

Sang-Hyeok Chu2, Woorham Bae2, Gyu-Seob Jeong2, Jiho Joo1, Gyungock Kim1, Deog-Kyoon Jeong2

1Electronics and Telecommunications Research Institute, South Korea.

2Seoul National University, South Korea.


This paper presents a 26.5 Gb/s optical receiver with an all-digital CDR (ADCDR) fabricated in a 65 nm CMOS process. The receiver consists of a transimpedance amplifier (TIA), a limiting amplifier (LA), and a half-rate ADCDR. The TIA and LA are based on an inverter-based amplifier for low power consumption. The ADCDR adopts an LC quadrature digitally controlled oscillator (LC-QDCO) for the quadrature sampling. The recovered clock jitter is 1.28 psrms and the measured jitter tolerance exceeds the tolerance mask specified in IEEE 802.3ba. The receiver sensitivity is measured to be -9 dBm and -6.6 dBm for the data rate of 25 Gb/s and 26.5 Gb/s, respectively. The whole receiver chip occupies an active area of 0.75 mm2 and consumes 254 mW at the data rate of 26.5 Gb/s.


Keywords: optical, receiver, transimpedance amplifier, all-digital clock and data recovery, LC quadrature digitally controlled oscillator




A 23mW/Lane 1.2-6.8Gb/S Multi-Standard Transceiver in 28nm CMOS

Seong-Ho Lee2, Duke Tran2, Tamer Ali2, Burak Catli2, Heng Zhang2, Wei Zhang2, Mohammed Abdul-Latif2, Zhi Huang2, Guansheng Li2, Mahmoud Ahmadi1, Afshin Momtaz2

1Altera, United States.

2Broadcom, United States.


This paper describes the design of a low power multi-standard transceiver in 28nm CMOS technology.  Using novel circuit techniques and implementation features, the transceiver can operate at data rates of 1.2-6.8Gb/s while supporting a wide range of communication standards, including SGMII, QSGMII, PCIE, SATA, USB3, XAUI and RXAUI.  Power consumption per lane is 23mW at 0.9V for SATA3  at 6Gb/s, with an area of 0.265mm2 for a single-lane transceiver with PLL.


Keywords: high speed integrated circuits, transceivers, serializer-deserializers, clock and data recover




Fully-Integrated 40-Gb/S Pulse Pattern Generator and Bit-Error-Rate Tester Chipsets in 65-nm CMOS Technology

Chin-Yang Wu2, Guan-Sing Chen2, Chen-Lun Lin1, Hao-Wei Hung1, Jri Lee2

1National Taiwan University, Taiwan.

2National Taiwan University, Atilia Technology, Taiwan.


Fully-integrated 40-Gb/s pulse pattern generator (PPG) and bit-error-rate tester (BERT) chipsets has been presented in 65-nm CMOS technology. Using external clock inputs, the PPG and BERT achieve full operation with ultra-wide data range from 40 Mb/s to 40 Gb/s. Built-in PLL and CDR circuits are also included to provide robustness for standard specification testing.


Keywords: Wide Range Pattern Generator, Bit Error Rate Tester, Full Rate Linear PD, CDR




A Power Management Unit Integrated ADSL/ADSL2+ CPE Analog Front-End with -93.5dB THD for DMT-Based Applications

Yu-Kai Chou2, Yue Feng2, Yu-Hsin Lin2, Cong Liu2,Chen-Yen Ho2, Bo Hu2, Jun Zha2, Steven Chuang1

1Econet Inc., Taiwan.

2Mediatek Inc., China.


This paper presents a high linear analog front-end  (AFE) for ADSL/ADSL2+ system applications.  This AFE has the overall linearity of -93.5dB to ensure the ADSL/ADSL2+ modem to achieve up to 27.2Mbps down-stream data-rate on short loops.  The AFE is implemented in two chips using 0.11um/55nm CMOS process with integrated power management unit (PMU) to optimize the data-rate, die area and power efficiency.  The choice of the process is a compromise between the size of the digital circuits, and the analog performance and cost.  Furthermore, a 90dB dynamic range (DR) CTSDM ADC is employed to relax the requirement of the front-end filters of the receiver, and thus the filter orders are reduced as well as the area and power consumption.  The transmit path can achieve 90dB SNR and -95.2dB THD. The receive path can achieve 82.1dB SNR and -93.5dB THD. The AFE including line driver using the dual-chip solution dissipates 590 mW from 3.3V/5 V supply.


Keywords:ADSL,AFE,DMT,PMU,ADC,DAC,Filter,analog front end




Session                               08: Panel

Date / Time                       November 11, 2014 (Tuesday) / 16:00-18:00 hrs

Venue                                 Opal Ballroom, 38F


TITLE                                   What is a Good Way to Expand a Silicon Value to a Solution Value?


Organizer/Co-organizer:           Tzi-Dar Chiueh, National Taiwan University, Taiwan

Toru Shimizu, Renesus, Japan

Moderator:                                  Gregory Chen, Intel, USA

Panelists / Position                    Chen Yi Lee, National Chiao Tung University/Medical and Healthcare

Charles Hsu, eMemory/Security in IoT

Tihao Chiang, Ambarella Taiwan/Video and Surveillence

Zhi-Hwa Wang, Tsinghua University/IoT and Healthcare

Dae Seok Byeon, Samsung Electronics Co./PC

Jongwoo Lee, Samsung/Mobile

Yasumoto Tomita, Fujitsu Laboratories/Interconnect

Takayuki Kawahara, Tokyo University of Science/Memory System


Abstract: The market sizes of each IoT application are relatively smaller than the PC and smartphone, although the development and production cost of the LSIs are becoming high. The LSI designers should find the ways to get funding of their development. One way is to get funding from providing system solution or service applications with expanding business models from supplying devices, as well as reducing the LSI costs and making the production volume larger. The pressure to expand the device supplying model depends on each application market, so such status of each application is to be discussed and also whether the expansion of the model is really necessary and practical or not.


Day 3     Wednesday, November 12, 2014


Session                               09: Plenary

Date / Time                       November 12, 2014 (Wednesday) / 08:30-10:05 hrs

Venue                                 Diamond II, 41F


[Plenary Talk 3]

TITLE                                   Semiconductor Innovation into the Next Decade

DATE / TIME                       November 12, 2014 (Wednesday) / 08:30-09:15 hrs

SPEAKER                             Jack Sun, VP/CTO, TSMC, Taiwan

Dr. Sun has been the mastermind behind the success of TSMC logic R&D in providing the most energy-efficient, high-density, high-throughput, and cost-effective CMOS platform and mixed-signal/RF technologies since 0.25um for logic/SOC products and the fabless industry, incl. massive parallel processors like GPU, GP-GPU, and server CPU; high gate-count FPGA; and multi-core (ARM/GPU) application processors for smart phone / mobile computing.  He proposed a System Scaling concept and figure of merit, encompassing Si wafer-based CMOS scaling, integrated specialty, and 3D chip stacking technology, to extend  "Superchip" and system scaling beyond 2020.


Dr. Sun had four IBM invention achievement awards and several IBM Outstanding Technical Accomplishment Awards in the 1990's.  He received "Ten Most Outstanding Engineer Award" of the Chinese Institute of Engineers in 2000.   He is a co-recipient of "Outstanding Technology Worker Award" from ROC Executive Yuan in 2003 for his leadership and technical contributions in the foundry-leading 0.13um low-power and high performance CMOS technology with world-leading Cu/Low-K interconnects.   He won the National Management Excellence Award in 2004.  He received 2010 ECE Distinguished Alumni Award from University of Illinois.  He also won TSMC Medal of Honor in 2011. Dr. Sun is an IEEE Fellow for his contributions to CMOS technology.  He received BSEE degree from National Taiwan University, and MS and Ph.D. degree from the University of Illinois.  He has over 200 papers, many invited and plenary talks, 12 US patents, and several ROC patents.


Abstract: Mobile computing has been the electronic industry growth driver over the past few years, with monolithic CMOS scaling (Moore's Law) being a key enabler.  "Giga-trends", or the "Next Big Thing", such as converged smart devices (i.e.: personal "Command and Control Center") ubiquitously connected to wearables and the internet of things (IoT), with big data and cloud computing as the backbone, will continue to enhance future lifestyles and drive the growth of the silicon-based nano-electronics industry.


Going forward, our vision is to realize  Energy-Efficient System Scaling that will make systems faster, smaller, lighter, thinner, and consume less power.  CMOS scaling (Moore's Law) will continue to be the central pillar of energy-efficient system scaling, with many innovation opportunities and challenges ahead.  Two other key system scaling pillars are novel integrated specialty technology and wafer-based 3D chip stacking.  CMOS scaling is like the brain, specialty technology like the five senses and human limbs, and 3D chip stacking like the spine of a human body.  Through this system scaling approach, the era of silicon-based "super system chips" has arrived.


Open and synergistic collaborative innovation is key to technical and business success under the new System Scaling paradigm.  TSMC's Grand Alliance and Open Innovation platform (OIP) represent a thriving symbiotic, synergistic, and powerful collaborative ecosystem for the "Next Big Thing" and the continued growth of the silicon-based nano-electronic industry.  With its  ecosystem partners and suppliers, the TSMC Grand Alliance supports the largest combined R&D investment and innovative power to drive the energy-efficient super system chips that will  enrich the future human experience.  


[Plenary Talk 4]

TITLE                                   Energy Efficient Computing in Nanoscale CMOS: Challenges and Opportunities

DATE / TIME                       November 12, 2014 (Wednesday) / 09:20-10:05 hrs

SPEAKER                             Vivek De, Intel, USA

Vivek De is an Intel Fellow and Director of Circuit Technology Research in Intel Labs. He is responsible for providing strategic technical directions for long term research in future circuit technologies and leading energy efficiency research across the hardware stack. He has 220 publications in refereed international conferences and journals and 193 patents, with 30 more patents filed (pending). He received an Intel Achievement Award for his contributions to an integrated voltage regulator technology. He received a PhD in Electrical Engineering from Rensselaer Polytechnic Institute, Troy, New York. He is a Fellow of the IEEE.


Abstract: Future computing systems spanning exascale supercomputers to wearable devices demand orders of magnitude improvements in energy efficiency while providing desired performance. The system-on-chip (SoC) designs need to span a wide range of performance and power across diverse platforms and workloads. The designs must achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS process while supporting a wide voltage-frequency operating range with minimal impact on die cost. We will discuss circuit and design technologies to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations. The major pillars of energy-efficient SoC designs are: (1) circuit/design optimizations for fine-grain multi-voltage & wide dynamic range, (2) fine-grain on-die power delivery & management, (3) dynamic adaptation & reconfiguration, and (4) dynamic on-die error detection & correction. Experimental results from research prototypes in advanced CMOS technologies will be presented.


Session                               10: Memory Technology

Date / Time                       November 12, 2014 (Wednesday) / 10:25-12:30hrs

Venue                                 Agate+Pearl, 42F

Chair                                   Chun Shiah, Etron Technology, Taiwan

Co-Chair                             Junghwan Choi, Samsung Electronics, Korea




A 16.8Gbps/Channel Single-Ended Transceiver in 65nm CMOS for Sip Based DRAM Interface on Si-Carrier Channel

Hyunbae Lee, Taeksang Song, SangyeonByeon, Kwanghun Lee, Inhwa Jung, Seongjin Kang, Ohkyu Kwon, KoeunCheon, DonghwanSeol, Jongho Kang, Gunwoo Park, Yunsaing Kim

SK hynix, South Korea.


A 16.8Gbps/channel single ended transceiver for SiP based DRAM interface on silicon carrier channel is presented. A transmitter, receiver, and channel are all included in a single package. On the transmitter, 1 tap FFEs are used in 4:1 MUX and in output driver. On the receiver, source follower based CTLEs and self Vref generator are used for obtaining effective single ended signaling on Si-carrier channel. A BER that is less than 1e-12 is achieved in 65nm CMOS. The power efficiency of the transceiver is 5.9pJ/bit with 120Ω terminations at each transceiver side.


Keywords:SiP based DRAM Interface, Single Ended Transceiver, FFE, CTLE, Self Vref Generator, BER and 120Ω terminations




0.339fJ/Bit/Search Energy-Efficient TCAM Macro Design in 40nm LP CMOS

Po-Tsang Huang2, Shu-Lin Lai2, Ching-Te Chuang2, Wei Hwang2, Jason Huang1, Angelo Hu1, Paul Kan1, Michael Jia1, Kimi Lv1, Bright Zhang1

1Faraday Technology Corporation, Taiwan.

2National Chiao Tung University, Taiwan.


In this paper, a 256x40 energy-efficient ternary content addressable memory (TCAM) macro is designed and implemented in 40nm low power (LP) CMOS.  Due to the thicker gate oxide in LP process, a 16T TCAM cell with p-type comparison circuits is proposed to increase the Ion/Ioff difference of the dynamic circuitry. To further improve energy efficiency, don't-care-based ripple search-lines/bit-lines are used to reduce both the switching activities and wire capacitance. Moreover, column-based data-aware power control is employed for leakage power reduction and write-ability improvements. The experimental results show a leakage power reduction of 28.9%, a search-line power reduction of 31.74% and an energy efficiency metric of the TCAM macro of 0.339 fJ/bit/search.


Keywords: Embedded memory, energy-efficient, TCAM




A Non-Volatile Look-Up Table Using ReRAM for Reconfigurable Logic

Wen-Pin Lin1, Shyh-Shyuan Sheu1, Pei-Ling Tseng1, Meng-Fan Chang2, Chia-Chen Kuo1

1Electronics and Optoelectronics Research Laboratories (EOL), ITRI, Hsinchu, Taiwan, Taiwan.

2National Tsing Hua University, Hsinchu, Taiwan, Taiwan.


This study demonstrated a nonvolatile look-up table (nvLUT) that involves using resistive random access memory (ReRAM) cells with normally-off and instant-on functions for suppressing standby current. Compared with the conventional static random access memory (SRAM)-magnetoresistive random-access memory (MRAM)-hybrid LUTs the proposed ReRAM-based two-input nvLUT circuit decreases the number of transistors and the area of nvLUT by 79% and 90.4%, respectively. The areas of the two- and three-input ReRAMnvLUTs are 11.5% and 74.2% smaller than the other MRAM-based two-input and PCM-based three-input LUTs, respectively. Because of the low current switching and high R-ratio characteristics of ReRAM, the proposed ReRAM-based nvLUT achieves 24% less power consumption than that of SRAM-MRAM-hybrid LUTs. The functionality of the fabricated adder of the three-input ReRAMnvLUT was confirmed using an HfOx-based ReRAM and a 0.18-μm complementary metal-oxide semiconductor with a delay time of 900 ps.


Keywords: Look-Up-Table, ReRAM, RRAM, FPGA, Reconfigurable Logic




A 6-Bit Drift-Resilient Readout Scheme for Multi-Level Phase-Change Memory

Aravinthan Athmanathan2, Milos Stanisavljevic1, Junho Cheon3, Seokjoon Kang3, Changyong Ahn3, Junghyuk Yoon3, Minchul Shin3, Taekseung Kim3, Nikolaos Papandreou1, Haris Pozidis1, Evangelos Eleftheriou1

1IBM Research, Switzerland.

2IBM Research/EPFL, Switzerland.

3SK, South Korea.


Multiple-Level Cell (MLC) storage provides increased capacity and hence reduced cost-per-bit in memory technologies, thereby rendering such technologies suitable for big data applications. In Phase-Change Memory (PCM), however, MLC storage is seriously hampered by the phenomenon of resistance drift. We present a readout circuit for PCM specifically designed for drift resilience in MLC operation. Drift resilience is achieved through the use of specific non-resistance-based cell-state metrics which, in contrast to the traditional cell-state metric, i.e., the low-field electrical resistance, have built-in drift robustness. The proposed read circuitry is designed and fabricated in 64-nm CMOS technology. Experimental results using an integrated test resistor array for readout circuit characterization are presented, demonstrating access time of 450 ns at 6-bit raw (5-bit effective) resolution. The circuit has low-noise characteristics and does not exhibit sensitivity to bit-line parasitics. The readout circuit is co-integrated with a 16 Mb 2x-nm PCM cell array and the necessary programming electronics.


Keywords: MLC PCM, Drift Resilience, Readout scheme




0.2 V 8T SRAM with Improved Bitline Sensing Using Column-Based Data Randomization

Anh-Tuan Do2, Zhaochuan Lee2, Bo Wang2, Ik-Joon Chang1, Tony Tae-Hyoung Kim2

1Kyunghee University, South Korea.

2NTU, Singapore.


8T SRAMs operating at sub-threshold supply voltages suffer from bit-line swing degradation when data pattern on the same column is dominated by "1" or "0". Worst case scenario happens when the accessed bit is different from the rest of the column. In this work, a simplified Linear Feedback Shift Register (LFSR) is used to shuffle input data so that distribution of "1" and "0" in each column is close to 50%. As a result, bit-line sensing margin is enhanced. Furthermore, a bit-line boost biasing scheme is applied to increase the bit-line swing and the sensing window. A 16Kb test chips fabricated in a 65 nm CMOS technology demonstrates successful SRAM operation at 0.2 V, room temperate, having power consumption and access time of 0.7 μW and 2.5 μs, respectively.


Keywords: Memory, SRAM, CMOS, low-voltage




A Configurable 2-in-1 SRAM Compiler with Constant-Negative-Level Write Driver for Low Vmin in 16nm Fin-FET CMOS

Ching-Wei Wu, Ming-Hung Chang, Chia-Cheng Chen, Robin Lee, Hung-Jen Liao, Jonathan Chang

Taiwan Semiconductor Manufacturing Company (TSMC), Taiwan.


This paper presents a configurable SRAM for low voltage operation supporting both pseudo two-port SRAM (P2P-SRAM) and single-port SRAM (SP-SRAM) functions in one compiler. Unlike conventional pseudo two-port SRAM that always performs read first, this work enables dynamic read-or-write-first selection and write-through function. It can improve SP-SRAM function speed by 90% faster than that of the conventional read-first pseudo two-port SRAM design. An area-free constant-negative-level write driver (CNL-WD), which is suitable for compiler development, is used to improve write Vmin for configuration range from 4 to 256 cells/BL. A testchip is fabricated in a 16nm Fin-FET CMOS technology with a 0.0907μm2 6T-SRAM cell.


Keywords: pseudo two-port SRAM, configurable, low Vmin, negative-level, compiler


Session                               11: Sensor Applications

Date / Time                       November 12, 2014 (Wednesday) / 10:25-12:30hrs

Venue                                 Diamond III, 41F

Chair                                   Po-Chiun Huang, National Tsing Hua University, Taiwan

Co-Chair                             Seung-TakRyu, KAIST, Korea



A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor with a Resolution FoM of 0.52 pJoC2

Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin

National Taiwan University, Taiwan.


A thermistor-embedded continuous-time delta-sigma modulator (CTDSM) implementing a temperature sensor (TS) is proposed in this paper. By embedding the resistor-based temperature sensing module into a 2nd-order 1-bit CTDSM, the proposed TS achieves high resolution sensing with reduced hardware complexity and power consumption. Furthermore, a resistor-ladder trimming and compensation scheme is proposed to facilitate the 1-point temperature calibration. The proposed TS is fabricated in a 0.18-um CMOS process. Over a range of -45 oC ~ 125 oC, this TS achieves 0.01 oCrms temperature resolution with 100-μs conversion time, which results in a resolution FoM of 0.52 pJoC2.


Keywords: Temperature Sensor, Continuous-Time Delta-Sigma Modulator, Thermistor-Embedded, Temperature-Independent Trimming




An Area-Efficient Capacitively-Coupled Instrumentation Amplifier with a Duty-Cycled Gm-C DC Servo Loop in 0.18-μm CMOS

Chih-Chan Tu, Feng-Wen Lee, Tsung-Hsien Lin

National Taiwan University, Taiwan.


A chopped capacitively-coupled instrumentation amplifier (CCIA) with a proposed duty-cycled Gm-C DC servo loop (DSL) for bio-potential signal acquisition is presented. The proposed architecture realizes a large time constant with small circuit area without sacrificing noise and power performance. Furthermore, this pseudo-resistor-less design grants this architecture easily portable for more advanced processes. Fabricated in a 0.18-μm CMOS, this chip draws 2.37 μA from a 1.8-V supply and occupies only an active area of 0.43 mm2. The total integrated noise from 0.5 to 100 Hz is 1.04 μVrms and results in a noise efficiency factor of 7.8.


Keywords: CCIA, Area-Efficient, Duty-cycled Gm-C, DSL




Highly Improved SNR Differential Sensing Method Using Parallel Operation Signaling for Touch Screen Application

SanghyunHeo, Hyunggun Ma, Jae Joon Kim, Franklin Bien

UNIST, South Korea.


In this paper, a continuous-time differential type multi-signal parallel driving architecture touch screen sensing circuit for projective capacitive type panel is presented. In order to further enhance the Signal-to-Noise Ratio (SNR), a new transmitter (TX) architecture is proposed with parallel signal processing algorithm. In this work, charge amplifiers with built in band-pass filter are designed that filter out low frequency noise and common-mode noise simultaneously. Conventional approaches in continuous-time operation with band-pass filter suffer from a synchronization problem in the case of multi-signal parallel driving.  In this work, a built-in delay calibration circuit is proposed that can align signal timing for TX signal and adjacent receiver (RX) sensing line. This proposed architecture enables multi-signal parallel driving in continuous-time operation for projective capacitive sensing circuits. The proposed work supports 16 x 8 mutual capacitive touch screen panel (TSP). TSP load is 12.5 kΩ and 40 pF with frame rate of 200 Hz and 58 dB SNR. Power dissipation is 46 mW.


Keywords: Touch Screen Panel, differential sensing, parallel operation, Band pass filter.




A 16.6μW 32.8MHz Monolithic CMOS Relaxation Oscillator

Yat-Hei Lam, Seong-Jin Kim

Institute of Microelectronics, Singapore.


This paper presents a 32.8MHz low power, supply insensitive monolithic CMOS relaxation oscillator. Instead of using voltage-mode comparators for cycle-to-cycle capacitor voltage swing (CVS) threshold voltage comparison, the CVS is regulated by a low-power closed-loop control which consists of a current-controlled delay cell (CCDC), a Gm-C error integrator and a comparator-free switch logic block. The CCDC and switching logics are powered by a logic supply regulator for reducing switching-losses and line sensitivity. The oscillator consumes 16.6μW from a 1.5V supply voltage at room temperature, achieving a FOM of 0.51μW/MHz. The measured output frequency variation is <±0.13%/V @ 32.8MHz, for a supply range of 1.5V to 3.6V. It occupies 0.013mm2 in a 0.18μm CMOS process.


Keywords: Relaxation oscillator, Low-power, Delay-Cell, Clock Generator, Power Efficiency, FOM, Capacitor Voltage Swing




An Ultra-Compact, Untrimmed CMOS Bandgap Reference with 3σ Inaccuracy of +0.64% in 16nm FinFET

Chin-Ho Chang, Jaw-JuinnHorng, Amit Kundu, Chih-Chiang Chang, Yung-Chow Peng

Taiwan Semiconductor Manufacturing Company (TSMC), Taiwan.


An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm2) that achieves medium accuracy (3σVBG 1.67%) without trimming.  The second bandgap aims at high-accuracy applications (area 0.013 mm2) that achieve 3σVBG 0.64% without trimming.  Both bandgap circuits have good TC performance less than 35ppm/°C between -40°C to 12°C. We claim to have the smallest chip area and highest accuracy when compared to the present state-of-the-art untrimmed CMOS bandgap circuits.


Keywords:Bandgap voltage reference, FinFET circuit, stack gate, MOS array layout, current mirror, opamp


Session                               12: mm-wave and THz

Date / Time                       November 12, 2014 (Wednesday) / 10:25-12:30hrs

Venue                                 Amber+Coral, 42F

Chair                                   Minoru Fujishima, Hiroshima University, Japan

Co-Chair                             Jenny Yi-Chun, National Tsing Hua University, Taiwan



CMOS THz Transmissive Imaging System

Tzu-Chao Yan, Chun-Hsing Li, Chih-Wei Lai, Wei-Cheng Chen, Tzu-Yuan Chao, Chien-Nan Kuo

National Chiao Tung University, Taiwan.


This paper presents a THz imaging system composed of a signal source and a signal sensor in CMOS technology. The signal source integrates a 338 GHz oscillator in 40-nm CMOS and an antenna array on a Benzocyclobutene (BCB) carrier using the SoP (System-on-Package) technique. The measured EIRP achieves +8 dBm. The signal sensor is implemented in 0.18 um CMOS. The measured maximum responsivity is 632 kV/W at 332 GHz. The signal source and signal sensor consume dc power of 37.5 mW and 7.92 mW, respectively. The resolution of the proposed THz imaging system is 4 mm.


Keywords: THz imaging system, CMOS, signal source, signal sensor, System-on-Package (SoP)




23Gbps 9.4pJ/Bit 80/100GHz Band CMOS Transceiver with on-Board Antenna for Short-Range Communication

Kensuke Nakajima3, Akihiro Maruyama3, Masato Kohtani3, Tsuyoshi Sugiura3, Eiichiro Otobe3, Jaejin Lee2, Shinhee Cho2, Kyusub Kwak2, Jeongseok Lee2, Toshihiko Yoshimasu4, Minoru Fujishima1

1Hiroshima University, Japan.

2Samsung Electric Corp., South Korea.

3Samsung R&D Institute Japan, Japan.

4Waseda University, Japan.


Fully integrated 80GHz-band and 100GHz-band transceiver ICs using 65nm CMOS technology and on-board antennas for high-speed/short-range wireless communication system are demonstrated. To realize higher speed and lower power consumption than those of a 60GHz-band standard application such as IEEE802.11ad, a simple transceiver architecture with non-coherent amplitude shift keying (ASK) modulation method using W-band (75-110GHz) is adopted. The aggregate 80/100GHz-band transceiver modules demonstrate 23Gbps over 10mm wirelessly with power consumption of 216mW. The developed transceiver modules achieve the highest speed of wireless communications above 60GHz-band and show a potential for future applications of 100Gbps high-speed short-range communications.


Keywords: CMOS, Millimeter-wave, Transceiver, Antenna, Data rate




A 3 Gb/S 64-QAM E-Band Direct-Conversion Transmitter in 40-nm CMOS

Dixian Zhao, Patrick Reynaert

KU Leuven, Belgium.


This paper describes a fully integrated E-band transmitter (TX) in 40-nm CMOS. Circuit, layout and calibration techniques are presented to suppress the LO feed-through (LOFT) and I/Q imbalance over both 71-76 and 81-86 GHz bands. A systematic design methodology is proposed for the millimeter-wave poly-phase filter (PPF) to achieve lowest I/Q imbalance with minimum EM simulations. The 40-nm E-band transmitter achieves a measured output power of 12.5 dBm and TX efficiency of 16% with more than 15 GHz bandwidth. Measured from 3 chips, the transmitter features an un-calibrated I/Q imbalance of less than -30 dB from 62.5 to 85.5 GHz. The calibration circuits further reduce the I/Q imbalance by 3-5 dB and ensure the LOFT less than -30 dBc over more than 30 dB output dynamic range. The presented TX achieves 3-Gb/s 64-QAM across the complete E-band.


Keywords: E-band, transmitter, power amplifier, poly-phase filter, mixer,  I/Q imbalance, LO feed-through, calibration, CMOS




A 0.015-mm2 60-GHz Reconfigurable Wake-Up Receiver by Reusing Multi-Stage LNAs

Rui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa

Tokyo Institute of Technology, Japan.


An area-efficient 60-GHz wake-up receiver (WuRx) using reconfiguration techniques of multistage low-noise amplifiers (LNAs) is presented. The gain stages of the 60-GHz LNA are reused as the envelope detectors for the wake-up receiver. Therefore, the bulky components such as extra switches between the wake-up receiver and the LNA, additional antennas, and excess input matching network can be removed in the design of the wakeup receiver. Furthermore, due to the reconfigurability of the LNA, the wake-up receiver can work in sensitivity-boost mode by using several LNA gain stages as a pre-amplifier. The wake-up receiver is fabricated in a 65-nm CMOS process occupying a core area of 0.015mm<sup>2</sup> (excluding the LNA). The WuRx achieves the sensitivity of -46dBm and -60dBm with a power consumption of 64μW and 12.7mW, respectively.


Keywords: CMOS, 60-GHz wake-up receiver, area-efficient, LNA-reused




54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB Gain Using Transformer Feedback Gm-Boosting Technique

Shita Guo1, Tianzuo Xi1, Ping Gui1, Jing Zhang3, Wooyeol Choi3, Kenneth K.O3, Yanli Fan2, Daquan Huang2, Richard Gu2, Mark Morgan2

1Southern Methodist University, United States.

2Texas Instruments, United States.

3University of Texas at Dallas, United States.


This paper presents a novel topology of low-noise amplifier (LNA) with noise reduction and gain improvement. A transformer feedback gm-boosting technique is proposed in a single-ended cascode LNA to reduce the noise figure (NF) and improve the gain simultaneously. Two 54 GHz single-ended cascode LNAs, with transformer and transmission-line for matching, respectively, are demonstrated to verify this technique. Fabricated in a 65 nm CMOS process, the transformer-based (TF-based) LNA exhibits a minimum noise figure (NF) of 3.6 dB at 53.5 GHz and a highest power gain of 28.2 dB at 54 GHz in measurement. To our best knowledge, this LNA has the best noise figure and power gain among all the published V-band CMOS LNAs. The transmission-line-based (TL-based) LNA exhibits a minimum noise figure of 3.8 dB at 53.9 GHz and a highest power gain of 25.4 dB at 54.2 GHz in measurement.  Both the LNAs consume 18 mA from a power supply of 1.1 V.


Keywords: Low-noise amplifier (LNA), noise figure (NF), power gain, transformer, transmission-line, V-band.


Session                               13: Biomedical Circuits and Systems

Date / Time                       November 12, 2014 (Wednesday) / 10:25-12:30hrs

Venue                                 Diamond II, 41F

Chair                                   Jerald Yoo, Masdar Institute of Science and Technology, UAE 

Co-Chair                             Shuenn-Yuh Lee, National Cheng-Kung University, Taiwan 



A 0.5-V Sub-uW/Channel Neural Recording IC with Delta-Modulation-Based Spike Detection

Seong-Jin Kim2, Lei Liu3, Lei Yao2, Wang Ling Goh3, Yuan Gao2, Minkyu Je1

1DGIST, South Korea.

2Institute of Microelectronics, Singapore.

3Nanyang Technological University, Singapore.


A neural recording IC with a new spike detection scheme is proposed to minimize power dissipation while preserving the waveform information of the detected spikes. A delta modulator is employed in the recording IC to reduce signal dynamic range and enable low-voltage operation. A series of output values from the delta modulator are stored in a small amount of analog memory to extract two key features of the neural signal  amplitude and frequency, which are used for accurate spike detection. Using the stored delta values, the precise spike waveform information can be conserved. A prototype recording IC with 16 channels has been fabricated using 0.18-um CMOS technology. Measurement results demonstrate the spike detection capability successfully. The fabricated IC consumes only 0.88 uW/channel at 0.5-V supply.


Keywords: neural recording, low power, low voltage, delta modulator, analog memory, spike detection




A 10.4 mW Electrical Impedance Tomography SoC for Portable Real-Time Lung Ventilation Monitoring System

Sunjoo Hong, Jaehyuk Lee, JoonsungBae, Hoi-Jun Yoo

KAIST, South Korea.


An electrical impedance tomography (EIT) SoC is proposed for the portable real-time lung ventilation monitoring system. The proposed SoC is integrated into belt-type EIT system with 32 electrodes and can show the dynamic images of the lung ventilation on the mobile devices. It has 3 key building blocks; 1) a T-switch for high off isolation > 60 dB between electrodes, 2) a I/Q signal generation and demodulation for high fidelity image, and 3) an on-chip fast demodulation scheme to reduce scanning time and ADC speed. As a result, real and imaginary part of images can be reconstructed with 97.3% of accuracy and can be displayed on the mobile devices. The proposed EIT SoC of 5.0 mm x 5.0 mm is fabricated in 0.18 um CMOS technology, and consumes only 10.4 mW with 1.8 V supply.


Keywords: Electrical impedance tomography, ventilation monitoring, complex impedance, low power




A Closed-Loop Power-Efficient Neural Recorder with Automatic Bandwidth Adjustment

Jian Xu, Zhi Yang

National University of Singapore, Singapore.


This paper presents a frequency-shaping neural recorder with automatic closed-loop bandwidth adjustment for power reduction. To optimize input noise, a novel gain boosting technique is used. Besides, an unsupervised EC-PC spike processor has also been integrated, which can reliably report spike firing rate: when the channel contains no spike activities, the recorder bandwidth is automatically reduced to output LFPs only, which gives 72% power saving for that channel. Measured at an 80kHz sampling clock and 1.0V supply, the recorder achieves a 3pF input capacitance, 2.2uV input noise for recording spikes, and maximum 15uW/ch total power. Empirical studies with in-vivo recordings have shown 70% of channels do not contain spikes, suggesting an averaged recording power reduction by 50% to 7.5uW/ch.


Keywords:Nerual Recorder, Frequency Shaping, Closed-Loop Control, Automatic Bandwidth Adjustment




A 20V-Compliance Implantable Neural Stimulator IC with Closed-Loop Power Control, Active Charge Balancing, and Electrode Impedance Check

Lei Yao2, Jianming Zhao3, Peng Li2, Rui-Feng Xue4, Yong Ping Xu3, Minkyu Je1

1Daegu Gyeongbuk Institute of Science and Technology, South Korea.

2Institute of Microelectronics, Singapore.

3National University of Singapore, Singapore.

4Philips Research China, China.


An inductively powered implantable neural stimulator IC is presented in this paper. It features closed-loop power control, active charge balancing, and electrode impedance check functions. The stimulator IC is powered through 13.56MHz inductive link and supports 33.3kbps bi-directional telemetry with ASK for forward command transmission and LSK for backward data transmission, achieving 20V high compliance voltage, maximum 1.24mA stimulation current, and the resting potential of 50mV. The IC has an active area of 2mm by 2mm implemented in 0.18-μm CMOS process with 24V LDMOS option.


Keywords: Neural stimulator, high-compliance-voltage, inductive power link, closed-loop power control, active charge balancing, electrode impedance check




A 330uW, 64-Channel Neural Recording Sensor with Embedded Spike Feature Extraction and Autocalibration

Alberto Rodriguez-Perez2, Manuel Delgado-Restituto2, Angela Darie2, Cristina Soto-Sanchez1, Eduardo Fernandez-Jover1, Angel Rodriguez-Vazquez2

1CIBER-BBN / University Miguel Hernandez, Spain.

2IMSE-CNM / University of Seville, Spain.


This paper reports a 64-channel neural recording sensor array. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements a local auto-calibration mechanism which configures the transfer characteristics of the recording site. The system has two operation modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are transmitted. Data streams coming from the channels are serialized by an embedded digital processor. Experimental results show that the power consumption of the complete system is 330uW.


Keywords: Neural recording, spike detection, low-power, low-voltage, ADC, low-noise amplifier, data compression

Session                               14: SoC and Signal Processing Techniques

Date / Time                       November 12, 2014 (Wednesday) / 13:30-15:35hrs

Venue                                 Diamond II, 41F

Chair                                   Kyung Ki Kim, Daegu University, Korea

Co-Chair                             An-Yeu Wu, National Taiwan University, Taiwan




A 27mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor

Injoon Hong2, Gyeonghoon Kim2, Donghyun Kim2, Byeong-Gyu Nam1, Hoi-Jun Yoo2

1chungnam university, South Korea.

2kaist, South Korea.


A marker-less Camera Pose Estimation Engine (CPEE) with reconfigurable logarithmic processor is proposed for the view angle estimation in the low-power mobile Augmented Reality (AR) applications. The proposed CPEE is required to overcome 150x huge gap in computational cost for marker-less pose estimation including floating-point operations resulting in the bottlenecks in mobile platforms. Speculative Execution (SE) and Reconfigurable Data-arrangement Layer (RDL) are proposed to reduce the computing time of CPEE by 17% and 27%, respectively. For low-power implementation of floating-point units, Logarithmic Processing Element (LPE) is used to reduce overall power consumption by 18%. The proposed marker-less CPEE is fabricated in 65nm Logic CMOS technology, and successfully realizes real-time marker-less camera pose estimation with only 27mW power consumption.


Keywords: reconfigurable SIMD, logarithmic number system, camera pose estimation, augmented reality, bundle adjustment, PTAM




A 4.9 mW Neural Network Task Scheduler for Congestion-Minimized Network-on-Chip in Multi-Core Systems

Youchang Kim, Gyeonghoon Kim, Donghyun Kim, Hoi-Jun Yoo

KAIST, South Korea.


A neural network task scheduler (NNTS) is proposed for the congestion-minimized network-on-chip in multi-core systems. The NNTS is composed of a near-optimal task assignment (NOTA) algorithm and a reconfigurable precision neural network accelerator (RP-NNA). The NOTA adopting a neural network is proposed to predict and avoid the network congestion intelligently. And the RP-NNA is implemented to improve the throughput of NOTA with dynamically adjustable precision. In the case that the NNTS is integrated into a NoC-based multi-core SoC for the augmented reality applications, 79.2% prediction accuracy of NoC communication pattern is achieved and the overall latency is reduced by 24.4%. As a result, the RP-NNA consumes only 4.9 mW and improves the energy efficiency of system by 22.7%.


Keywords: network-on-chip (NoC), network congestion, task assignment, neural network (NN)




An 87 × 49 Mutual Capacitance Touch Sensing IC Enabling 0.5 mm-diamater Stylus Signal Detection at 240 Hz-Reporting-Rate with Palm Rejection

Shinichi Yoshida, MutsumiHamaguchi, Takahiro Morishita, Shinji Shinjo, Akira Nagao, Masayuki Miyamoto

Sharp Corporation, Japan.


A touch sensing system capable of stylus input should have "palm rejection" function which allows a user to place one's palm on the surface of the touch sensor while writing with a stylus. A simple and effective technique to realize "palm rejection" function is implemented in a newly developed mutual capacitance touch sensing IC. Furthermore, in order not to report unwanted touches due to large palm signals, a palm detection filter is introduced.


Keywords: mutual capacitance, touch sensing, stylus, palm rejection, alternating drive




A 2.5W Tablet Speaker Delivering 3.2W Pseudo High Power by Psychoacoustic Model Based Adaptive Power Management System

Shin-Hao Chen, Ke-Horng Chen

EE, National Chiao Tung University, Taiwan.


for a 2.5W speaker in tablets, the proposed adaptive power management (APM) system can deliver a pseudo high power of 3.2W with a ±4V supply because it suppresses 0.7W power on tones that may damage a 2.5W speaker and escape the notice of human ears. With z-domain digital signal processing (z-DSP) and psychoacoustic model, high efficient power management and high sound quality can be achieved simultaneously. Conventional automatic gain control (AGC) only has the ability of 0.32W power suppression. Moreover, suppressing power by conventional clipping technique increases total-harmonic-distortion (THD). In contrast, the proposed real-time dynamic loading impedance (RT-DLI) monitoring brings forward a way to solve the problem on speaker damage while keeping low THD during high sound pressure level (SPL). THD in the APM system is slightly higher than that of original sound 1.1dB, comparing to the disadvantage of 8.6dB increasing caused by conventional clipping technique.


Keywords: power suppression, psychoacoustic model, speaker protection, class D audio amplifier, digital signal processing




An Intermittent-Driven Supply-Current Equalizer for 11x and 4x Power-Overhead Savings in CPA-Resistant 128bit AES Cryptographic Processor

Noriyuki Miura, Daisuke Fujimoto, RieKorenaga, Kohei Matsuda, Makoto Nagata

Kobe University, Japan.


A supply-current equalizer disables a Correlation Power Analysis (CPA) attack on an AES cryptographic processor. An intermittent operation only at processing rounds critical to key disclosure suppresses the equalizer power overhead almost one order of magnitude. For this low-power intermittent operation, a Thru operation mode is proposed with minimum hardware overhead. A level-shift comparator hides its own power consumption in an internal equalized virtual supply to guarantee secure protection of a secret key. Test-chip measurement in 0.18μm CMOS successfully demonstrates CPA-attack resiliency. The equalizer power overhead is reduced to 1/11 which is only 8% of 128bit AES processor power consumption.


Keywords: hardware security, cryptography, side-channel attack




A 1-100Mb/S 0.5-9.9mW LDPC Convolutional Code Decoder for Body Area Network

Chih-Lung Chen, Sheng-Jhan Wu, Hsie-Chia Chang, Chen-Yi Lee

National Chiao Tung University, Taiwan.


A low power LDPC convolutional code decoder is implemented in 90nm CMOS technology. The proposal demonstrates a novel FEC candidate based on shift/shared memory architecture for the IEEE 802.15.4g and 802.15.6 body area network applications. Measurement shows the test chip achieves (1) 1 to 100Mb/s with power consumption of 0.5 to 9.9mW under 0.6V supply voltage (2) better error correcting performance compared with Viterbi decoder under same silicon area.


Keywords: LDPC-CC, Body Area Network, Low Power


Session                               15: Analog Circuits and Systems

Date / Time                       November 12, 2014 (Wednesday) / 13:30-15:10hrs

Venue                                 Diamond III, 41F

Chair                                   Tetsuya Hirose, Kobe University, Japan

Co-Chair                             Li-Ren Huang, Industrial Technology Research Institute, Taiwan




A 1V Input 3-to-6V Output Integrated 58%-Efficient Charge-Pump with Hybrid Topology and Parasitic Energy Collection for 66% Area Reduction and 11% Efficiency Improvement

Jen-Huan Tsai, Sheng-AnKo, Hui-Huan Wang, Chia-Wei Wang, Po-Chiun Huang

National Tsing-Hua University, Taiwan, Taiwan.


This paper presents a low-area, high-efficiency hybrid 6-stage voltage multiplier by cascoding Dickson charge-pumps and modified Cockcroft-Walton charge-pumps, and paralleling them with auxiliary charge-pumps. The proposed architecture obtains a good area and efficiency performance without using high-V devices or external capacitors. Implemented in standard 0.18-μm CMOS process, the prototype provides a wide output range of 3-6V and 30-240μA load from a 1-V supply with an efficiency of 48-58% (52% at 6V). By using on-chip MOS capacitors as internal pumping capacitors, a 66% area reduction is gained. The area shrinks to 0.05mm2 per 9× interleaved cell. The efficiency loss due to parasitics is compensated by creating auxiliary parasitic pumping pathes to collect parasitic energy. With this feed-forward parasitic charge-pump, the efficiency increases extra 11%. Higher efficiency is thus measured than most reported on-chip Dickson CPs and cascodeddoublers of comparable gain.


Keywords: Charge-pump, Switched-capacitor, DC-DC boost converter, voltage multiplier, high-voltage, MOSCAP




A 12-V Charge Pump-Based Square Wave Driver in 65-nm CMOS Technology

Yousr Ismail, Chih-Kong Ken Yang

UCLA, United States.


This paper presents a high-voltage output stage producing signals well beyond the voltage ratings of standard devices in a nanometer-scale CMOS technology. The driver composes of a two-level, switched capacitor output stage that combines both voltage-conversion and pulse-drive. The design is highly modular and enables extended device stacking seamlessly with little overhead. The design achieves a peak power efficiency of 64%, a minimum drive resistance of 3.7KΩ and occupies an area of 0.06mm2.


Keywords: Charge pumps, driver circuits, high-voltage techniques, transistor stacking




A Programmable Discrete-Time Filter Employing Hardware-Efficient Two-Dimensional Implementation Method

Jaeyoung Choi, M. Kumarasamy Raja, M. AnnamalaiArasu

Institute of Microelectronics, A-STAR, Singapore.


A programmable discrete-time (DT) filter for wideband wireless systems is presented. A 2-dimensional FIR implementation reduces the complexity by creating a convolution between charge-sharing and charge-accumulation filters. The filter down-converts the input over a wide frequency while limiting the variation in the output rate, by programming the decimation factor in proportion to the carrier frequency. The filter is fabricated in 65nm CMOS for a proof-of-concept in 100-300MHz. When the decimation factor is selected to be proportional to the input frequency, variation ranges of gain and bandwidth were narrow as 56.8-59.1dB and 1.22-1.27MHz. The filter rejects aliasing frequencies more than 35dB.


Keywords: discrete-time filter, wideband, switched-capacitor filter, reconfigurable, software-defined radio (SDR)




A Low-Input-Swing AC-DC Voltage Multiplier Using Schottky Diodes

Ye-Sing Luo, Shen-Iuan Liu

National Taiwan University, Taiwan.


A low-input-swing AC-DC voltage multiplier using Schottky diodes is presented. The equivalent model of the voltage multiplier is developed and analyzed. To enhance power conversion efficiency (PCE), a matching network is added. For a multiple-stage voltage multiplier, a limiting circuit is added for over-voltage protection. A single-stage/three-stage voltage multiplier with a limiting circuit is fabricated in a 0.18μm CMOS technology and its area is equal to 0.761mm^2. With the matching network, the measured maximum PCE are 31.4% and 35.8% when input amplitudes are 60mV and 160mV for a single-stage voltage multiplier and a three-stage one, respectively, at input frequency of 1MHz.


Keywords:Schottky Diode, Voltage Multiplier


Session                               16: RF Systems

Date / Time                       November 12, 2014 (Wednesday) / 13:30-15:35hrs

Venue                                 Amber+Coral, 42F

Chair                                   Chun HuatHeng, National University of  Singapore, Singapore

Co-Chair                             Ting-Ping Liu, Nokia, USA




A 0.1-5GHz Flexible SDR Receiver in 65nm CMOS

Xinwang Zhang, Baoyong Chi, Yang Xu, Bingqiao Liu, Qian Yu, Siyang Han, Qiongbing Liu, Zehong Zhang, Yanqiang Gao, Zhihua Wang

Institute of Microelectronics, Tsinghua University, China.


A 0.1-5GHz flexible software-defined radio (SDR) receiver is presented with three RF front-end paths (Main/Sub/HR paths). Main path and sub path can reject out-of-band blockers and harmonic interferences, and feature low NF and high linearity, respectively. Harmonic rejection (HR) path can effectively reject the harmonic interferences with simple calibration mechanism. Dual feedback LNA, class-AB Op-Amp with miller feed-forward compensation and quasi-floating gate (QFG) techniques, reconfigurable continuous-time (CT) low pass (LP) and complex band pass (CBP) sigma-delta ADC are proposed. This chip has been implemented in 65nm CMOS with 9.6-47.4mA current consumption from 1.2V voltage supply and a core chip area of 5.4mm2. The receiver main path achieves 3.8dB NF, +5dBm/+5dBm IB-IIP3/OB-IIP3 as well as +58dBm IIP2. The sub path achieves +10dBm/+18dBm IB-IIP3/OB-IIP3 as well as +61dBm IIP2. And it offers RF filtering with 10dB rejection at 10MHz offset. The HR path achieves +13dBm/+14dBm IB-IIP3/OB-IIP3 and >54/56dB 3rd/5th-order harmonic rejection with 30-40dB rejection improvement by calibration.


Keywords: SDR, Receiver, Sigma-Delta ADC, LNA, Op-Amp




A 1.44mm2 4-Channel UWB Beamforming Receiver with Q-Compensation in 65nm CMOS

Lei Wang, Yong Lian, Chun HuatHeng

National University of Singapore, Singapore.


A compact 4-channel UWB beamforming receiver is proposed by employing low-Q LC delay with Q-compensation technique. The delay chain achieves 224 ps delay range with 7 ps delay resolution. It occupies area of 1.44 mm2, which is 7 times smaller than other UWB beamformer with LC delay. To compensate the losses generated by low Q inductors and minimize the power consumption, current reuse LNA and buffers are adopted. The receiver covers scanning angle of ±48° with spatial resolution of 4° under antenna spacing of 3 cm while consuming 288 mW.


Keywords: UWB beamforming receiver, wideband phase shifter, current reuse LNA, current reuse buffer, noise cancelling LNA




A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communication in 180nm CMOS

Xiaobao Yu, Meng Wei, Yun Yin, Ying Song, Siyang Han, Qiongbing Liu, ZongmingJin, Xiliang Liu, Zhihua Wang, Baoyong Chi

Institute of Microelectronics, China.


A fully-integrated reconfigurable dual-band transceiver for short range wireless communication has been implemented in 180nm CMOS. In Sub-GHz band, the maximum 75dBc 3rd HRR is achieved by using a RFA with notch filtering. In 2.4GHz band, a single-ended-to-differential RFA with phase and gain error compensation is proposed. Class-C VCOs are employed in the Σ-Δ fractional-N PLL to save the power. Moreover, multi-mode CMOS PAs with power-control loops are proposed to enhance the efficiency at back-off powers.


Keywords: CMOS, wireless transceiver, short range wireless communications, harmonic rejection, power amplifier, PAPR




A 0.65V 0.95mW 2.4GHz/400MHz Dual-Mode Phase Modulator for Mobile Healthcare Applications

Yang Li2, Ni Xu2, Yining Zhang2, Woogeun Rhee2, Sanghoon Kang1, Zhihua Wang2

1Samsung, South Korea.

2Tsinghua University, China.


A 0.65V 2.4GHz/400MHz digital-intensive phase modulator is implemented in 65nm CMOS. In ultra-low voltage design, the two-point modulator suffers a lot from the DCO nonlinearity. In this work, we employ a 2.4GHz semidigital fractional-N PLL with an FIR filter embedded 1-bit high-pass modulation to overcome the nonlinearity problem in the conventional two-point modulator. The 400MHz modulator performs an FIR-embedded OQPSK modulation to reduce the spectral regrowth in high frequencies. For compact area and low voltage design, an inverter based phase interpolator with a harmonic filtering technique is designed after generating multiphase signals directly from the 2.4GHz output. The 1Mb/s GFSK 2.4GHz and the 10Mb/s OQPSK 400MHz modulators consume 0.94mW and 1.2mW and achieve the EVM values of 5.7% and 6.4% respectively.


Keywords: wireless transceiver, RF, ultra-low power, ultra-low voltage, phase modulator




An Ultra-Low-Power RF Transceiver with a 1.5-pJ/bit Maximally-Digital Impulse-Transmitter and an 89.5-uW Super-Regenerative RSSI

Hiroyuki Ito2, Shoichi Masui1, Youichi Momiyama1, Yoshihiro Yoneda2, Taiki Ibe2, Taisuke Hamada2, Noboru Ishihara2, Kazuya Masu2

1Fujitsu Laboratories Ltd., Japan.

2Tokyo Institute of Technology, Japan.


This paper proposes an RF transceiver with a maximally-digital impulse transmitter (I-TX) and a super-regenerative received-signal-strength-indicator (RSSI) circuit for wireless sensor network application. Our I-TX enables strict bit-level duty cycling operation to achieve both ultra-low power consumption and superior energy-per-bit in kb/s to Mb/s range. The proposed RSSI for low-power localization and low-rate downlink measures input power by exploiting the phenomenon that the oscillation start-up time logarithmically accelerates as input power increases. The I-TX fabricated in a 65nm CMOS achieves 1.5 pJ/bit at 10 Mb/s. The RSSI with -85 dBm sensitivity consumes 89.5 uW with modest dynamic range and linearity.


Keywords: RF CMOS, Sensor Network




A 103 pJ/Bit Multi-Channel Reconfigurable GMSK/PSK/16-QAM Transmitter with Band-Shaping

Xiayun Liu2, Yuan Gao1, Wei-Da Toh1, San-Jeow Cheng1, Minkyu Je1, Chun-Huat Heng2

1Institute of Microelectronics, ASTAR, Singapore.

2National University of Singapore, Singapore.


This paper presents a 401~406 MHz GMSK/PSK/16-QAM TX for biomedical application. Using DLL based phase interpolated synthesizer and injection-locked ring oscillator, we achieve fine frequency tuning and multi-phase output without any need of phase calibration. Through direct quadrature modulation at the digital PA, the TX achieves less than 6% EVM for data rate up to 12.5Mb/s. The band-shaping maximizes spectral efficiency with ACPR of -33dB. Consuming 2.57mW, the TX achieves energy efficiency of 103pJ/bit.


Keywords: transmitter, reconfigurable, injection locking, band shaping,energy efficiency


Session                               17: Equalizer and Clock Data Recovery

Date / Time                       November 12, 2014 (Wednesday) / 13:30-15:35hrs

Venue                                 Agate+Pearl, 42F

Chair                                   Jun Terada, Nippon Telegraph and Telephone, Japan

Co-Chair                             Chao-Cheng Lee, Realtek, Taiwan



A 5-20 Gb/S Power Scalable Adaptive Linear Equalizer Using Edge Counting

Yuan-Fu Lin2, Chang-Cheng Huang2, Jiunn-Yih Lee1, Chih-Tien Chang1, Shen-Iuan Liu2

1MStar Semiconductor Inc, Taiwan.

2National Taiwan University, Taiwan.


A 5-20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The edge counting method adopts the proposed data rate detection circuit to adaptively adjust the bandwidth and power of the CTLE. For the wide data rate application, the power efficiency of the CTLE is improved.


Keywords: adaptive CTLE, power scalable




A 3.12 pJ/Bit, 19-27 Gbps Receiver with 2 Tap-DFE Embedded Clock and Data Recovery

Wei-Zen Chen, Zheng-Hao Hong

NCTU, Taiwan.


A 19-27-Gb/s receiver comprising of a continuous time linear equalizer (CTLE) followed by a 2 tap decision feedback equalizer embedded clock and data recovery circuit is implemented. The hybrid CDR is operated at half rate, which is incorporated into a broad band PLL to facilitate ISI and jitter suppression over wide band operation. A quadrature relaxation type oscillator is proposed to provide the sampling phases without bulky inductors. Fabricated in a 40 nm CMOS technology, the whole receiver manifests a high energy efficiency of   3.12pJ/bit at 27 Gbps operation to compensate 20 dB channel loss at Nyquist frequency. The core area is 0.09 mm2 only.


Keywords: CTLE, DFE, CDR, PLL




A 2X25 Gb/S Clock and Data Recovery with Background Amplitude-Locked Loop

Chien-Kai Kao, Kuan-Lin Fu

National Taiwan University, Taiwan.


A 2X25 Gb/s clock and data recovery circuit is fabricated in a 40-nm CMOS process. A background amplitude-locked loop is proposed to reduce the amplitude variation of a charge-steering-logic return-to-zero latch. The measured rms jitter is 2.26 ps and the peak-to-peak jitter is 15.56 ps for a 25 Gb/s PRBS of 27-1. It dissipates 8.8 mw per channel from 1.15 V supply.


Keywords: Clock and Data Recovery




A 0.011 mm2 PVT-Robust Fully-Synthesizable CDR with a Data Rate of 10.05 Gb/S Using Injection-Locking Technique

AravindTharayil Narayanan, Wei Deng, Yang Dongsheng, Wu Rui, Kenichi Okada, Akira Matsuzawa

Tokyo Institute of Technology, Japan.


This paper presents a fully synthesized clock and data recovery circuit using injection locking technique. The challenges presented by automated place and route for high speed applications is overcome using background calibration mecha- nism. The fully-synthesizable all-digital architecture presented in this work is fabricated in 28nm FDSOI technology. The system has a top data-rate of 10.05Gb/s while consuming 16mW power from 1.0V suppy.


Keywords: CDR, Injection-locking, synthesizable




A 6-Gb/S Adaptive-Loop-Bandwidth Clock and Data Recovery (CDR) Circuit

Li-Hung Chiueh, Tai-Cheng Lee

National Taiwan University, Taiwan.


An adaptive circuit is proposed to adjust CDR loop bandwidth based on different jitter spectral profile for better jitter performance. The preventional lock detector (PLD) is employed to achieve better jitter suppression ability without jitter tolerance (JTOL) degradation. The proposed circuit enhances the jitter suppression by 14.14 dB at an 8-MHz sinusoidal jitter source. This adaptive block is fully-digital synthesized and the whole circuit consumes 86.4 mW for a 6-Gb/s input data.


Keywords: jitter suppression,jittertolerance,adaptive loop bandwidth


Session                               18: Circuit Techniques for Emerging Applications

Date / Time                       November 12, 2014 (Wednesday) / 15:55-18:00hrs

Venue                                 Diamond II, 41F

Chair                                   Shinichiro Mutoh, Nippon Telegraph and Telephone, Japan

Co-Chair                             YoungcheolChae, Yonsei University, Korea




A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms Response Humidity Sensor for Respiratory Monitoring

Kelvin Yi-Tse Lai, Yu-Tao Yang, Bang-Jing Chen, Chun-Jen Shen, Ming-Feng Shiu, Zih-Cheng He, Hsie-Chia Chang, Chen-Yi Lee

National Chiao-Tung University, Taiwan.


An event-driven and energy-efficient humidity sensor for environment detection and healthcare monitoring is presented. A differential CMOS-MEMS humidity device and proportion-based capacitance-to-digit readout circuit are proposed to overcome PVT variations, and in the meantime to improve sensitivity, response time, and conversion energy. This chip achieves 15.6b 20-90 %RH at 1KS/s, 6.1pJ per 0.02%RH of sensitivity, and 10ms fast response time in TSMC 0.35-μm CMOS MEMS process. With variations in temperature and voltage, our proposal can minimize the errors from 40%RH to 0.2%RH and 50%RH to 0.1%RH, making it very suitable for wearable respiratory monitoring.


Keywords: Humidity Sensor, Capacitive Sensing, Low Power/ Energy, Respiratory Monitoring, Healty-Care




A 5.2mW IEEE 802.15.6 HBC Standard Compatible Transceiver with Power Efficient Delay-Locked-Loop Based BPSK Demodulator

Hyunwoo Cho, Hyungwoo Lee, JoonsungBae, Hoi-Jun Yoo

KAIST, South Korea.


A low power fully IEEE 802.15.6 HBC compatible transceiver is implemented in 0.13μm CMOS process. The transmitter uses an analog active filter instead of digital type filter to remove the power-hungry high speed DAC and clock generation. In the receiver, a power-efficient delay-locked-loop (DLL) based BPSK demodulator is adopted to relax the stability problem of synchronization feedback loop. The sample and hold operation in the control voltage of the DLL enables the receiver to turn off the synchronization circuits during the hold time, leading to over 30% power reduction. The energy detection ability with Received Signal Strength Indicator (RSSI) detector for MAC operation adjusts the operating mode of LNA and even reconfigures the receiver architecture for power-efficient operation, resulting in over 70% power saving. As a result, the proposed transceiver can fully satisfy the HBC standard while consuming 4.3mA from the 1.2V supply.


Keywords: IEEE 802.15.6, HBC, BPSK, DLL-based demodulator, RSSI, active filter




A 0.4V 280-nW Frequency Reference-Less Nearly All-Digital Hybrid Domain Temperature Sensor

Wenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang

National University of Singapore, Singapore.


This paper presents a subthreshold frequency reference-less temperature sensor. Compared with the previous designs that rely on external frequency references or excessive analog blocks, this work proposes a novel subthresholdratioed-current/delay sensor core and hybrid-domain all-digital processing technique, which eliminates the dependence on frequency reference and is scalable to technology feature size. Our sensor has been fabricated in a 65-nm CMOS process and occupies a total area of 0.022mm^2. Measurement results from 8 test chips have shown that the maximum inaccuracy is -1.6 oC/+ 1oC across 0 oC to 100 oC with power consumption of 280nW at 0.4V.


Keywords:Subthreshold, temperature sensor, frequency reference, hybrid domain




A 135 μW 0.46mΩ/√Hz Thoracic Impedance Variance Monitor with Square-Wave Current Modulation

Chih-Chan Tu, Feng-Wen Lee, Dong-Feng Yeih*, and Tsung-Hsien Lin

National Taiwan University, Taiwan.

*Cardinal Tien Hospital, Taipei, Taiwan.


Abstract - A low-power high-resolution thoracic impedance variance (TIV) monitoring circuit is presented. The TIV information is extracted by injecting a square-wave modulated current to the body. The resulted voltage is then demodulated by a proposed delayed-sampling technique. This proposed technique solves the gain-error issue occurred in prior square-wave modulated architectures. Furthermore, compared with sine-wave modulation, the proposed TIV monitoring circuit is more power efficient. Fabricated in a 0.18-μm CMOS, this chip draws 75 μA from a 1.8-V supply. The equivalent input-referred impedance noise density is only 0.46 mΩ/√Hz.


Keywords: Thoracic Impedance Variance, Square-wave Modulation




A 10μA on-Chip Electrochemical Impedance Spectroscopy System for Wearables/Implantables

JingrenGu, Huanfen Yao, BabakParviz, Brian Otis

University of Washington, United States.


This work proposes a new time-domain integration method to realize Electrochemical Impedance Spectroscopy (EIS). Unlike traditional EIS systems which use a quadrature sinusoid stimulus, we propose a low-frequency, low-amplitude sinusoid stimulus, which is realized through a sinusoid DAC without the need for analog filter. The error caused by harmonic generation can be suppressed through integration in detection. The response current is sensed by a switched capacitor integrator with control synchronized with sinusoid DAC. The integration output is sampled and digitized by an 8-bit SAR ADC. The (1×1.1)mm^2 prototype is fabricated in a 130nm CMOS process. It consumes 10μA from a 1.2V supply.


Keywords: Electrochemical Impedance Spectroscopy, sinusoid DAC, time-domain integration




22.5 dB Open-Loop Gain, 31 Khz GBW Pseudo-CMOS Based Operational Amplifier with a-IGZO TFTs on a Flexible Film

Koichi Ishida2, Reza Shabanpour2, Bahman Boroujeni2, Tilo Meister2, Luisa Petti1, Niko Mnzenrieder1, Giovanni Salvatore1, Corrado Carta2, Gerhard Tr"ster1, Frank Ellinger2

1Swiss Federal Institute of Technology Zurich, Switzerland.

2Technische Universit„t Dresden, Germany.


This paper presents an operational amplifier integrated in a flexible a-IGZO TFT technology. The circuit consists of only nMOS transistors, and the pair of active loads is in a pseudo-CMOS configuration. The amplifier is fabricated on a flexible film, and characterized with 5 V supply voltage and an output load capacitance of 15 pF. The measured open-loop gain is 22.5 dB, which is the highest reported for operational amplifiers in metal-oxide TFT technology. The measured bandwidth and gain bandwidth products are 5.6 kHz, and 31 kHz, respectively with 160 μW power consumption, which is lowest among flexible operational amplifies.


Keywords: Flexible, a-IGZO TFT, operational amplifier, active load, low power


Session                               19: Low Power ADCs

Date / Time                       November 12, 2014 (Wednesday) / 15:55-17:35hrs

Venue                                 Diamond III, 41F

Chair                                   Tai-Cheng Lee, National Taiwan University, Taiwan

Co-Chair                             Liyuan Liu, Chinese Academy of Sciences, China



A 0.022mm2 98.5dB SNDR Hybrid Audio Delta-Sigma Modulator with Digital Eld Compensation in 28nm CMOS

Tze-Chien Wang, Yu-Hsin Lin, Chun-Cheng Liu

Mediatek, Taiwan.


In this paper, a hybrid ΔΣ modulator with 6-bit shared asynchronous successive approximation register (ASAR) quantizer for audio application is proposed in 28nm CMOS process. The modulator incorporates a 1st-order analog filter and a 1st-order digital filter, which enables highly integration of digital signal processing at low power and small area. The 1st-order digital filter is developed to reduce the area significantly by replacing the conventional analog 2nd integrator. Moreover, the proposed digital filter provides digital excess loop delay (ELD) compensation which eliminates the conventional analog ELD feedback DAC. In addition, R-DAC is adopted to alleviate the flicker noise in 28nm process. The measured result shows 98.5dB SNDR and 100.6dB DR within 24kHz bandwidth, while occupying 0.022mm2 and achieving aFoM of 343fJ/conv. (Power/(2BW·2ENOB)) or 173.8dB (DR+10*log(BW/Power)).


Keywords: delta sigma modulator




A 1V 59 fJ/Step 15 MHz BW 74 dB SNDR Continuous-Time ΔΣ Modulator with Digital Eld Compensation and Multi-Bit FIR Feedback

Yi Zhang2, Chia-Hung Chen2, Tao He2, Nancy Qian1, Ed Liu1, Phillip Elliott1, Gabor Temes2

1Maxim Integrated, United States.

2Oregon State University, United States.


A 3rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented.  A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit FIR feedback DAC permits the use of a noise transfer function with high out-of-band-gain, and reduces sensitivity to clock jitter. The modulator operates at 1.2 GHz, and achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies 0.16 mm2 and dissipates 6.96mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.


Keywords: Continuous-Time ΔΣ  Modulator, Excess Loop Delay compensation, Reference Switching, Multi-bit FIR Feedback




A 0.3V 10bit 7.3fJ/Conversion-Step SAR ADC in 0.18μm CMOS

Cheng-En Hsieh, Shen-Iuan Liu

National Taiwan University, Taiwan.


A 0.3V 10-bit rail-to-rail SAR ADC is realized in 0.18-μm CMOS technology without calibration. To operate for a 0.3-V supply, a DBS switch, a supply-boosted time-domain comparator, and the dynamic control circuit are presented. This ADC achieves the SNDR of 54.57dB and the SFDR of 69.89dB, respectively. The DNL and INL are +0.51/-0.62 LSB and +1.06/-1.05 LSB, respectively. The power consumes 15.9nW at 5kS/s from a 0.3V supply. A figure-of-merit of 7.3fJ/conversion-step for this ADC is achieved.


Keywords: successive approximation register, ADC, low supply voltage




A 10b 100kS/S SAR ADC with Charge Recycling Switching Method

Kai-Hsiang Chiang2, Soon-Jyh Chang2, Guan-Ying Huang1, Ying-Zu Lin1

1National Cheng Kung, Taiwan.

2National Cheng Kung University, Taiwan.


This paper presents a low-voltage and energy-efficient 10b SAR ADC which manipulates charge recycling switching method for saving the switching energy. In additional, a window-based reconfigurable comparator is used to achieve fast comparison and small power dissipation. The proposed 10b SAR ADC operates at 100kS/s with 0.4V supply voltage in 90nm CMOS. The measurement results show that the prototype ADC achieve 55.37dB SNDR at Nyquist rate with only 107nW. The Figure-of-Merit (FoM) is 2.23fJ/conv.-step


Keywords: SAR ADC, Charge Recycling


Session                               20: RF Building Blocks

Date / Time                       November 12, 2014 (Wednesday) / 15:55-18:00hrs

Venue                                 Amber+Coral, 42F

Chair                                   Baoyong Chi, Tsinghua University, China

Co-Chair                             Chien-Nan Kuo, Nationa Chao Tung University, Taiwan



RF Transconductor Linearization Technique Robust to Process, Voltage and Temperature Variations

Harish Kundur Subramaniyan1, Eric A.M. Klumperink1, Venkatesh Srinivasan2, Ali Kiaei3, Bram Nauta1

1IC-Design Group, University of Twente, Netherlands.

2Texas Instruments, Dallas, Texas, United States.

3Texas Instruments, Santa Clara, California, United States.


A new reconfigurable linearized low noise transconductance amplifier (LNTA) design for a software-defined radio receiver is presented. The transconductor design aims at realizing high linearity at RF in a way that is robust for Process, Voltage and Temperature variations. It exploits resistive degeneration in combination with a floating battery by-pass circuit and replica biasing to improve IIP3 in a robust way. The LNTA with current domain mixer is implemented in a 45nm CMOS process. Compared to an inverter based LNTA with the same transconductance, it improves PIIP3 from 2 dBm to a robust PIIP3 of 8 dBm at the cost of 67% increase in power consumption.


Keywords: CMOS,  Software-defined Radio, Receiver, Linearity, Transconductor, Transconductor Figure-of-Merit, PVT, robust circuit design




A Feedforward Noise and Distortion Cancellation Technique for CMOS Broadband LNA-Mixer

Cuei-Ling Hsieh, Chang-Ming Lai, Chi-Fu Li, Shih-Chieh Chou, Jenny Yi-Chun Liu, Po-Chiun Huang

National Tsing Hwa University, Taiwan.


This work presents a circuit technique for broadband LNA-mixer to improve the noise and distortion performance simultaneously. By introducing an auxiliary feedforward path that carries the LNA noise and third-order intermodulation distortion (IM3) with equal magnitude and opposite phase to mixer output, the overall noise and IM3 are reduced while the signal is enhanced. The power overhead is small compared to the conventional tradeoff between the power consumption and linearity performance. The test circuit using a 0.18μm CMOS process includes a shunt-feedback LNA and two cross-coupled active mixers. All the circuits consume 7.7 mA from a 1.8 V supply. The signal bandwidth is 2 GHz. At 900MHz the voltage gain and noise figure are 19 dB and 6.2 dB respectively. There is 2.7dB NF and 10.1dB IM3 improvements with only 15% power overhead.


Keywords: noise and distortion cancellation, linearization, low power, shunt-feedback, broadband.




An Ultra-Low-Cost ESD-Protected 0.65dB NF +10dBm OP1dB GNSS LNA in 0.18-Um SOI CMOS

FeiSong1, Chun Geik Tan2, Osama Shanaa1

1Mediatek USA Inc., United States.

2Mediatek Singapore Pte Ltd, Singapore.


an ESD-protected GNSS LNA, implemented in 0.18um SOI CMOS process, uses only one external series inductor as input matching. The input common-source transistor is biased in weak inversion region and operates at Class-AB mode, which greatly improves linearity and saves quiescent current. A bond wire to ground is adopted as source-degeneration and to realize input matching. Design trade-offs among NF, stability and ESD protection are analyzed. The LNA achieves an ultra-low NF of 0.65dB,  a power gain of 19.2dB,  an output P1dB of +10dBm, while consuming 5.9mA from 2.8V supply. The LNA is housed in a 6-pin LGA package with a die area (including pads) of 0.28mm2. It passes 2.5KV HBM, 200V MM and 250V CDM ESD tests.






A Frequency-Reconfigurable Multi-Standard 65nm CMOS Digital Transmitter with LTCC Interposers

Nai-Chung Kuo2, Bonjern Yang2, Chaoying Wu2, Lingkai Kong2, Angie Wang2, Michael Reiha1, Elad Alon2, Ali Niknejad2, Borivoje Nikolic2

1Nokia, United States.

2UC-Berkeley, United States.


This paper demonstrates a CMOS digital polar transmitter with flip-chip interconnection to low-temperature co-fired ceramic (LTCC) interposers. The LTCC interposers contain the PA output balun targeting different operating frequency bands, and the reconfiguration in the carrier frequency is achieved by selecting an appropriate LTCC interposer. The same CMOS core transmitter is re-used for different frequency bands.  In this design, an output power higher than 22 dBm from 0.6 to 2.4 GHz is demonstrated, with peak power of 27.1 dBm and peak efficiency of 52%. The polar transmitter includes 9-bit phase interpolation and 8-bit amplitude modulation, suitable and verified as a multi-standard universal digital modulator.


Keywords: digital polar modulation, digital transmitter, LTCC, CMOS, power amplifier




A 44.9% PAE Digitally-Assisted Linear Power Amplifier in 40 nm CMOS

Haoyu Qian, Jose Silva-Martinez

Texas A&M University, United States.


This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its efficiency. A fast switching scheme is proposed, such that PA segments are switched on and off according to signal power, i.e. the proposed scheme makes the PA power consumption correlates with the power of the input signal. Binary power gain variations due to segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the trade-off between efficiency and linearity by employing the digital predistortion technique. The PA is implemented in 40 nm CMOS process, it delivers a saturated output power of 35 dBm with 44.9% power-added efficiency (PAE) and linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at +/- 5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc.


Keywords: Power amplifier, Radio frequency, Linear power amplifier, Multimode power amplifier, CMOS power amplifier, RF power amplifier (PA)




A 0.1-1.5GHz Harmonic Rejection Receiver Front-End with Hybrid 8 Phase Lo Generator, Phase Ambiguity Correction and Vector Gain Calibration

Xinwang Zhang, Baoyong Chi, Zhihua Wang

Institute of Microelectronics, Tsinghua University, China.


A 0.1-1.5GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity, and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8 phase local oscillating (LO) generator, the highest carrier frequency from the frequency synthesizer is only twice of the desired LO frequency. The HR receiver has been implemented in 65nm CMOS. With 1.8mm2 core chip area and 5.4-24.5mA current consumption from a 1.2V power supply, the receiver achieves 85dB conversion gain, 4.3dB NF, +13dBm/+14dBm IB/OB-IIP3, >54/56 dB HR3/HR5 with 30-40dB improvement by calibration, and 2.3% EVM with 32QAM modulation signal.


Keywords: harmonic rejection, receiver, phase ambiguity, LO generator, vector gain calibration


Session                               21: High-speed Wireline Building Blocks

Date / Time                       November 12, 2014 (Wednesday) / 15:55-18:00hrs

Venue                                 Agate+Pearl, 42F

Chair                                   Bo Zhang, Broadcom, USA

Co-Chair                             Che-Fu Liang, Mediatek, Taiwan



A 50-Gb/S Differential Transimpedance Amplifier in 65nm CMOS Technology

Sang Gyun Kim2, Seung Hwan Jung3, Yun Seong Eo3, SeungHoon Kim1, Xiao Ying1, Hanbyul Choi1, Chaerin Hong1, Kyungmin Lee1, Sung Min Park1

1Ewha Womans University, South Korea.

2Kwangwoon University, South Korea.

3Silicon R&D, South Korea.


A 50-Gb/s differential transimpedance amplifier is realized in a standard 65nm CMOS process, which exploits asymmetric transformer peaking technique for bandwidth extension and employs a modified regulated-cascode input stage with a shunt-feedback common-source amplifier for differential signaling. Measured results demonstrate 52-dBmtransimpedance gain, 50-GHz bandwidth for 50fF photodiode capacitance, -12.3dBm sensitivity for 10-12 BER, and 49.2-mW power dissipation from a single 1.2-V supply. To the best of authors' knowledge, this chip achieves the fastest operation speed among the recently reported gigabit CMOS transimpedance amplifiers. The chip occupies the total area of 1.2×0.8mm2 including pad.


Keywords: CMOS, regulated-cascode, TIA, transformer




A 3 MHz-to-1.8 GHz 94 uW-to-9.5 mW 0.0153-mm2 All-Digital Delay-Locked Loop in 65-nm CMOS

Chun-Yuan Cheng1, Jinn-Shyan Wang2, Pei-Yuan Chou2, Shiou-Ching Chen2, Chi-Tien Sun1, Yuan-Hua Chu1, Tzu-Yi Yang1

1Industrial Technology Research Institute, Taiwan.

2National Chung Cheng University, Taiwan.


It is challenging to design a closed-loop all-digital delay-locked loop (ADDLL) that also has a small area, low power, and fast locking for a wide frequency range operation. In this work, a cyclic half-delay-line architecture with the same type of delay lines for cyclic delay deduction and coarse locking is proposed to achieve the design goals of small area and fast locking for a wide frequency range operation. In addition to clock gating, which is used to reduce power consumption in the lock-in state regardless of the clock frequency, automatic bypassing of the cyclic operation is developed to reduce power consumption for high-frequency operations. Based on these proposed techniques, a 3 MHz-to-1.8 GHz 94 uW-to-9.5 mW 0.0153-mm2 closed-loop ADDLL is realized in 65-nm CMOS.


Keywords: ADDLL, wide range, small area, low power




A 0.52-V 5.7-GHz Low Noise Sub-Sampling PLL with Dynamic Threshold MOSFET

Sho Ikeda, Sangyeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

Tokyo Institute of Technology, Japan.


This paper proposes a low voltage sub-sampling PLL with dynamic threshold MOSFET (DTMOS). DTMOS switch can achieve higher on/off ratio, which prevents signal attenuation and leakage of a sub-sampling phase detector (SSPD) under low supply voltage. The proposed SSPD also employs double-balanced structure to suppress feedthrough in hold mode. DTMOS switches are also applied to a sub-sampling charge pump to reduce undesirable current leak. The proposed PLL was fabricated in a 65nm CMOS. Under the power supply of 0.52V, it shows a in-band phase noise of -98 dBc/Hz at 410 kHz, and the total power consumption of 1.72mW at 5.71 GHz including frequency-locked loop.


Keywords: PLL, phase noise, sub-sampling




A Novel 2.4-to-3.6 GHz Wideband Subharmonically Injection-Locked PLL with Adaptively-Aligned Injection Timing

Zhao Zhang, Liyuan Liu, Nanjian Wu

Institute of Semiconductors, Chinese Academy of Sciences, China.


A novel wideband subharmonically injection-locked PLL (SILPLL) is proposed. It adopts a new injection timing alignment technique to adjust injection timing adaptively in wide range of the output clock frequency. A proposed pulse generator is used for half-integral injection to relax the trade-off between phase-noise of SILPLL and output frequency resolution. The SILPLL is implemented in 65nm 1P9M CMOS process. It consumes 9.1 mW from a 1.2V supply and occupies an active core area of 1×0.6 mm2. The measured output frequency range is 2.4~3.6GHz and the rms jitter integrated from 1kHz to 30MHz is 146fs when output frequency is 3GHz.


Keywords: Low jitter, half-integral injection, subharmonically injection-locked PLL (SILPLL), wideband, adaptively-aligned, injection timing



Asymmetric Frequency Locked Loop (AFLL) for Adaptive Clock Generation in a 28nm SPARC M6 Processor

YifanYanggong, Sebastian Turullols, Daniel Woo, Changku Hwang, King Yen, VenkatKrishnaswamy, KalonHoldbrook, Jinuk Shin

Oracle Inc., United States.


Oracle's SPARC M6 processor features an Asymmetric Frequency Locked Loop (AFLL) that dynamically adjusts chip frequency. It achieves 15% improved noise immunity by reacting to the voltage noise asymmetrically through the use of a pair of DCO's that accurately track the response of critical paths. The AFLL is implemented in 28nm CMOS process in 0.045mm2 of area, dissipating 14mW, and reducing jitter by 50%.


Keywords: Adaptive Clock Generator




A DC-46Gb/S 2:1 Multiplexer and Source-Series Terminated Driver in 20nm CMOS Technology

Jian Hong Jiang, Samir Parikh, Mark Lionbarger, Nikola Nedovic, Takuji Yamamoto

Fujitsu Laboratories of America, United States.


We present a 46Gb/s 2:1 multiplexer and a source series terminated full rate driver for high speed chip-to-chip communications. The multiplexer and the driver are implemented using the pseudo-differential static CMOS circuit. Transmitter driver uses the push-pull structure to produce a VDD peak-to-peak differential voltage swing. The circuit uses no current mode logic gates or large on-chip passive devices aside from series-connected on-chip resistor and the T-coil used to minimize the return loss. We confirmed the total jitter of about 7ps at 46Gb/s and eye opening of 0.605UI up to 50 Gb/s on the test circuit fabricated in 20nm CMOS technology. Measured power consumption is 38.7mW at 46Gb/s (0.84pJ/b power efficiency).


Keywords: multiplexer, source-series terminated driver, transmitter, CMOS, push-pull, termination, T-coil