Supporters & Exhibitors

Important Dates

Aug. 18, 2014
Acceptance notification

Sept. 15, 2014
Deadline for final paper submission
& Author registration deadline

Oct. 31, 2014
Slides due to session chairs

Nov. 9, 2014
Speaker rehearsal

Nov. 10-12, 2014

Local Time (GMT+8)

Taipei, Taiwan



Peter Kinget
Columbia University

Low-voltage Analog and RF Circuits in Scaled Technologies

Date: Nov. 10 (Mon), 2014
Wim Dehaene

Energy efficient digital design – a circuit's perspective

Date: Nov. 10 (Mon), 2014

Wing-Hung Ki

Design of On-Chip Switched-Capacitor Power Converters

Date: Nov. 10 (Mon), 2014
Ingrid Verbauwhede

Digital circuits and design techniques for security and cryptography

Date: Nov. 10 (Mon), 2014

Title Low-voltage Analog and RF Circuits in Scaled Technologies
Speaker Peter Kinget
Position Professor
Affiliation Columbia University
Time/Place Track 1: 09:00-10:20 Nov. 10 (Mon), 2014/Amber+Coral, 42F
Track 2: 10:40-12:00 Nov. 10 (Mon), 2014/Agate+Pearl, 42F
Peter Kinget is a Professor of Electrical Engineering at Columbia University, NY. He is also a consulting expert on patent litigation and a technical consultant to industry. His research interests are in analog, RF and power integrated circuits and the applications they enable in communications, sensing, and power manage-ment. He is a fellow of the IEEE, is widely published and received several awards. He has been a "Distinguished Lecturer" for the Solid-State Circuits Society, and an Associate Editor of the Journal of Solid State Circuits and the Transactions on Circuits and Systems II. He has served on the program committees of many of the major solid-state circuits conferences and is currently an elected member of the IEEE SSCS Adcom.

CMOS technology scaling has fueled tremendous progress in electronics and has enabled system-on-chip (SoC) products. Scaling increases the performance and density for digital signal processing, computation and memory. But, analog and RF circuits remain the critical interfaces to connect the digital cores of SoCs to the physical world and need to satisfy increasing performance demands. At the same time, designing analog and RF functions with sub-1V supply voltages in scaled processes is very challenging. This tutorial will start with reviewing the basic analog and RF low voltage challenges and how they force a rethinking of even the most basic circuit blocks. We will review design solutions to operate analog and RF circuits with supply voltages down to 0.5V. They range from exploiting the 4 terminals of the MOS device, to the use of circuit topologies that require only stacks of few devices, to the complete reengineering of the circuit architecture or even the use of different analog information representations. They will be illustrated with design examples of full analog and RF system functions.

Title Design of On-Chip Switched-Capacitor Power Converters
Speaker Wing-Hung Ki
Position Professor
Affiliation HKUST
Time/Place Track 1: 09:00-10:20 Nov. 10 (Mon), 2014/Agate+Pearl, 42F
Track 2: 10:40-12:00 Nov. 10 (Mon), 2014/Amber+Coral, 42F
Wing-Hung Ki received his BSc from University of California, San Diego (UCSD, 1984), MSc from California Institute of Technology (Caltech, 1985), and PhD from University of California, Los Angeles (UCLA, 1995), all in electrical engineering. From 1992 to 1995, he worked for Micro Linear, San Jose, on the design of power converter controllers. He joined the Hong Kong University of Science and Technology (HKUST) in 1995, and is currently a professor of the Department of Electronic and Computer Engineering. His research interests are IC techniques for power management circuits, power transponders for RFID and energy harvesting applications, and fundamental research in switching converters, charge pumps and analog IC techniques.

With the increasing demand of integrating voltage regulators completely on-chip, switched-capacitor power converters that consist of only capacitors and switches are gaining popularity as substitutes for inductor-based DC-DC converters. Switched-capacitor power converters (SCPCs) are often known as charge pumps, especially for those with voltage conversion ratios larger than unity. This tutorial starts with classifications of charge pumps. Charge balance law is then introduced, and charge redistribution loss is discussed. Topologies of step-up charge pumps are generated systematically using the ANTZ (all negative nodes to zero) principle, and efficiency optimization is presented. Gate control techniques, loss reduction considerations, single-branch, dual-branch and multi-phase implementations and step-down charge pumps will also be discussed.

Title Energy efficient digital design – a circuit's perspective
Speaker Wim Dehaene
Position Professor
Affiliation MICAS, KU Leuven & IMEC
Time/Place Track 1: 13:00-14:20 Nov. 10 (Mon), 2014/Amber+Coral, 42F
Track 2: 14:40-16:00 Nov. 10 (Mon), 2014/Agate+Pearl, 42F
Wim Dehaene received the M. Sc. degree in electrical and mechanical engineering in 1991 from the Katholieke Universiteit Leuven. In November 1996 he received the Ph. D degree at the Katholieke Universiteit Leuven. In November 1996 he joined Alcatel Microelectronics, Belgium. There he was a senior project leader for the feasibility, design and development of mixed mode Systems on Chip. The application domains were telephony, xDSL and high speed wireless LAN. In July 2002 Wim Dehaene joined the staff of the ESAT-MICAS laboratory of the Katholieke Universiteit Leuven where he is now a full professor. His research domain is circuit level design of digital circuits. The current focus is on ultra low power signal processing and memories in advanced CMOS technologies. Part of this research is performed in cooperation with IMEC, Belgium where he is also a part time principal scientist. Wim Dehaene is teaching several classes on electrical engineering and digital circuit and system design. He is also very interested in the didactics of engineering. As such he is guiding several projects aiming to bring engineering to youngsters and he is a teacher in the teacher education program of the KULeuven. Wim Dehaene is a senior member of the IEEE and served on the technical program committee of DATE, ESSCIRC and ISSCC.

In this tutorial the design of energy efficient digital circuit design will be addressed. The focus will be on transistor and gate level and eventually microarchitecture. The tutorial will start by introducing the problem: where does the energy go in digital circuits and why is energy efficiency even more of an issue as the CMOS technology becomes more advanced. This will put static leakage and device variability on the map. From there on several techniques to improve the energy efficiency will be explained. Both dynamic and static energy (leakage) will be dealt with. It will be shown that design strategies for energy efficiency are different for logic and memory design. Therefore design examples from both domains will be illustrated.

Title Digital circuits and design techniques for security and cryptography
Speaker Ingrid Verbauwhede
Position Professor
Affiliation COSIC, KU Leuven & UCLA
Time/Place Track 1: 13:00-14:20 Nov. 10 (Mon), 2014/Agate+Pearl, 42F
Track 2: 14:40-16:00 Nov. 10 (Mon), 2014/Amber+Coral, 42F
Ingrid Verbauwhede is a Professor in the research group COSIC of the EE Department of the KU Leuven in Belgium. At COSIC, she leads the embedded systems and hardware group. She is also adjunct professor at the EE department at UCLA, Los Angeles, CA. She has experience as a post-doctoral researcher and lecturer at UC Berkeley and she worked for TCSI and Atmel in Berkeley, CA. She received her MSc and PhD degree from KU Leuven in 1991. She is a Member of IACR and the Belgian Academy of Science and she is a fellow of IEEE. Her main interest is in the design and the design methods for secure embedded circuits and systems.

Her list of publications and patents is available at .

E-Health, e-commerce, smart meters, cyber physical systems, and many more, all need secure and efficient implementations of cryptography for their correct and trusted operation.

Implementing cryptographic algorithms into embedded devices, is a challenge for efficiency reasons as well as security reasons. Because the algorithms use unusual arithmetic, are computationally intensive and often use very large word lengths, it is difficult to fit them into the area, throughput, power and/or energy constraints. Moreover, the implementations have to be made resistant to a wide range of physical attacks, both invasive and non-invasive. Thus adding countermeasures to the implementations, adds an extra optimization goal. In this tutorial, implementations for efficiency as well as security of cryptographic algorithms will be covered.